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9th SIGDA Ph.D. Forum at DAC

Tuesday, July 25th, 2006 
Moscone Center 
San Francisco, CA 


Sponsored by
SIGDA
DAC
Supported by
Intel
IBM Research
STMicroelectronics
Synopsys
Cadence
Altera
Xilinx

TPC Chair
Frank Liu
  IBM, USA

TPC Co-Chair
Tony Givargis
  UC Irvine, USA

Publicity Chair
Ion Mandoiu
  Univ. Connecticut, USA

Finance Chair
Tony Givargis
  UC Irvine, USA

Past Chair
Radu Marculescu
   Carnegie Mellon Univ.
   USA

SIGDA Liaison
Robert B. Jones
   Intel, USA

Program Committee

Cristinel Ababei
  Magma, USA
Fadi Aloul
  Amer. Univ. Sharjah
  UAE
Iris Bahar
  Brown Univ., USA
Twan Basten
  Eindhoven Univ. Tech.,
  The Netherlands
Krish Chakrabarty
  Duke Univ., USA
Samarjit Chakraborty
  Natl. Univ., Singapore
Naehyuck Chang
  Seoul Natl. Univ., Korea
Vivek Chickermane
  Cadence, USA
Philip Chong
  Cadence, USA
Pasquale Cocchini
  Intel, USA
Katherine Compton
  Univ. Wisconsin, USA
Adam Donlin
  Xilinx, USA
Peter Feldmann
  IBM, USA
Tony Givargis
  UC Irvine, USA
Ian Harris
  UC Irvine, USA
Jiang Hu
  Texas A&M Univ., USA
Mike Hutton
  Altera, USA
Prabhakar Kudva
  IBM, USA
Guy Lemieux
  Univ. British Columbia,
  Canada
Peng Li
  Texas A&M Univ., USA
Ion Mandoiu
  Univ. Connecticut, USA
Subhasish Mitra
  Stanford Univ., USA
Kartik Mohanram
  Rice Univ., USA
Gi-Joon Nam
  IBM, USA
Michael Niemier
  Georgia Tech., USA
Davide Pandini
  ST Micro, Italy
Carl Pixley
  Synopsys, USA
Donatella Sciuto
   Politechnico di Milano
  Italy
Youngsoo Shin
  KAIST, Korea
Jin Yang
  Intel, USA

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Call for Participation

The Ph.D. Forum at the Design Automation Conference is a poster session hosted by SIGDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It has become one of the premier forums for Ph.D students in design automation to get feedback on their research and for industry to see academic work in progress: 400-500 people attended each of the last two forums.

The 2006 SIGDA PhD Forum at DAC will be held between 6:30-8:00pm on Tuesday, July 25th, 2006 in Room 310 of the Moscone Center in San Francisco, CA.

The forum is open to all members of the design automation community and is free-of-charge. It is co-located with DAC to attract the large DAC audience, but DAC registration is not required in order to attend this event.

Helpful links:


Accepted Submissions

Track 1: System-level synthesis and optimization

Thermal-Aware Synthesis and Sensing Techniques for Integrated Circuits
  Rajarshi Mukherjee
The Impact of Dynamic Voltage and Frequency Scaling on the Energy Consumption, Schedulability and Predictability of Real-Time Embedded Systems
  Bren C Mochocki
Systematic Synthesis of Analog and Mixed-Signal Systems
  Ewout Martens
Compositional Design Space Exploration
  Arne Hamann
Thermal-aware EDA Design
  Wei-Lun Hung
Property Synthesis
  Barbara Jobstmann
Communication-centric SoC Design for Nanoscale Domain
  Umit Y. Ogras
Design and Synthesis of Current-Mode High-Performance On-Chip Interconnect Signa ling in Nanometer Technologies
  Vishak Venkatraman
The Phantom Serializing Compiler
  Andre C Nacul
Dataflow-based Memory Optimization for DSP Software Synthesis
  Ming-Yung Ko
System-level Resource Management for Highly Constrained Embedded Systems
  Qiang Xie
A Performance Driven Approach for Hardware Synthesis of Guarded Atomic Actions
  Daniel L. Rosenband
Integration of Cache Coherence Protocols for MPSoCs and Coherence Traffic Evaluation using FPGA
  Taeweon Suh and Hsien-Hsin S. Lee

Track 2: Logic level synthesis and optimization

Novel Optimization Techniques for Leakage Minimization of Digital Circuits
  Sarvesh Bhardwaj
Computing Functional Properties and Network Flexibilities for Logic Synthesis and Verification
  Jin S. Zhang

Track 3: Physical Design

Variation and Power Issues in VLSI Clock Networks
  Ganesh Venkataraman
Modeling and Design Optimization Considering Nanometer Process Variation Effects
  Jinjun Xiong
Incremental Placement for Modern VLSI Design Closure
  Haoxing Ren
An Integrated Placement and Routing Approach for Large Scale Designs
  Min Pan

Track 4: Timing and noise analysis

Structural Macromodeling for Beyond-the-die Integration of High Performance Mixed-mode Systems
  Hao Yu
Stochastic Performance Analysis of Interconnects in the Presence of Manufacturing Process Variations
  Praveen Ghanta

Track 5: Verification

Automatic Formal Verification of Software Models vs. Hardware Implementations
  Xiushan Feng
Efficient Equivalence Checking of System-Level Designs Utilizing Textual Differences
  Takeshi Matsumoto
Formal Approaches to IP Composition
  Syed Suhaib
EQUIVALENCE VERIFICATION OF ARITHMETIC DATAPATHS USING FINITE RING ALGEBRA
  Namrata Shekhar

Track 6: Testing and failure analysis

New Techniques and Tools for Post-Silicon Timing Validation
  Kai Yang, Kwang-Ting Cheng
Efficient Testing of High-Performance Data Converters using Low-Cost Test Instrumentation
  Shalabh Goyal

Track 7: FPGA and reconfigurable systems

Supporting Heavily Pipelined Reconfigurable Computing on Commodity Devices
  Ken Eguro
Context-Free Grammar Parsing for High-Speed Network Applications in Reconfigurable Hardware
  James Moscola, Young H. Cho, John W. Lockwood
Heterogeneous FPGAs
  Peter Jamieson
Automatic Sliding Window Operation Optimization for FPGA-Based Computing Boards
  Haiqian Yu
Implications of Future Technologies on the Design and CAD of FPGAs
  Aman Gayasen
Synthesizing Efficient FPGA Implementations for DSP Applications
  Welson Sun

Track 8: CAD of emerging technologies

A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
  Chen He
Designing Reliable Nano-scale circuits using Markov Random Fields
  Kundan Nepal

Contact Information

For questions not addressed on this page, please send e-mail to: daforum@sigda.org.

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Sponsored By

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Supported By

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ST Logo Synopsys Logo
Cadence Logo Altera Logo
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Last modified May 2, 2006