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8th SIGDA Ph.D. Forum at DAC

Tuesday, June 14, 2005
Anaheim Convention Center
Anaheim, CA

Sponsored by
SIGDA
DAC
Supported by
Altera
Cadence
IBM
Intel
Philips
Synopsys
TPC Chair
Radu Marculescu
   Carnegie Mellon Univ.
   USA
TPC Co-Chair
Frank Liu
  IBM, USA
Finance Chair
Tony Givargis
  UC Irvine, USA
Publicity Chair
Ion Mandoiu
  Univ. Connecticut, USA
Past Chair
Robert Jones
  Intel, USA
SIGDA Liaison
Soha Hassoun
  Tufts Univ., USA
Program Committee

Cristinel Ababei
  Magma, USA
Fadi Aloul
  Amer. Univ. Sharjah, UAE
Iris Bahar
  Brown Univ., USA
Clark Barrett
  New York Univ., USA
Twan Basten
  Eindhoven Univ. Tech.,
  The Netherlands
Naehyuck Chang
  Seoul Natl. Univ., Korea
Samarjit Chakraborty
  Natl. Univ., Singapore
Pasquale Cocchini
  Intel, USA
Katherine Compton
  Univ. Wisconsin, USA
Peter Feldmann
  IBM, USA
Ian Harris
  UC Irvine, USA
Payam Heydari
  UC Irvine, USA
Jiang Hu
  Texas A&M Univ., USA
Mike Hutton
  Altera, USA
Prabhakar Kudva
  IBM, USA
Guy Lemieux
  Univ. British Columbia,
  Canada
Peng Li
  Texas A&M Univ., USA
Ken Mai
   Carnegie Mellon Univ.
   USA
Kartik Mohanram
  Rice Univ., USA
Gi-Joon Nam
  IBM, USA
Mike Niemier
  Georgia Inst. Tech., USA
Sule Ozev
  Duke Univ., USA
Davide Pandini
  ST Micro, Italy
Roberto Passerone
  Cadence, USA
Narendra Shenoy
  Synopsys,USA
Youngsoo Shin
  KAIST, Korea
Paul Stravers
  Philips, The Nederlands
Jin Yang
  Intel, USA
Sister Forums
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Call for Participation

The Ph.D. Forum at the Design Automation Conference is a poster session hosted by SIGDA for Ph.D. students to present and discuss their dissertation research with people in the EDA community. It has become one of the premier forums for Ph.D students in design automation to get feedback on their research and for industry to see academic work in progress: 400-500 people attended each of the last two forums.

The 2005 SIGDA PhD Forum at DAC will be held between 6:30-8:00pm on Tuesday, June 14, 2005 at the Anaheim Convention Center, Room 204 Foyer (the large hallway area outside room 204). The forum is open to all members of the design automation community and is free-of-charge. It is co-located with DAC to attract the large DAC audience, but DAC registration is not required in order to attend this event. Note that the Design Automation Summer School (DASS) will also be held in Anaheim, CA on June 10-11, 2005.

Helpful links:

Accepted Submissions

Track 1: Interconnect and timing analysis

Efficient Capacitance and Inductance Extraction of High Performance Integrated Circuits PDF Supporting Paper

Rong Jiang, University of Wisconsin - Madison (US)

Parallel Algorithms for Inductance Extraction of VLSI Circuits PDF Supporting Paper

Hemant Mahawar, Texas A&M University (US)

Statistical Static Timing Analysis: From Interconnect to Latch PDF Supporting Paper

Lizheng zhang, University of Wisconsin - Madison (US)

Track 2. Physical design

I-Xtreme: A Statistically-Based Engine for P/G Network Optimization PDF Supporting Paper

Dimitrios P. Karampatzakis, University of Thessaly (GR)

Layout Optimization in Ultra Deep Submicron VLSI Design PDF Supporting Paper

Di Wu, Texas A&M University (US)

mSMART: A Signal-integrity-, MAnufacturing-, Reliability-, and Timing-Driven Multilevel Full-Chip Routing PDF Supporting Paper

Tsung-Yi Ho, National Taiwan University (TW)

Research on Constraint-driven and Performance-driven Floorplanning Algorithm PDF Supporting Paper

Yuchun Ma, Tsinghua University (CN)

Robust Design using Parametric Statistical Optimization PDF Supporting Paper

Matthew R. Guthaus, University of Michigan (US)

Routability-Driven Placement for Timing and Power Optimization PDF Supporting Paper

Chen Li, Purdue University (US)

Statistical Clock Designs for Timing-Convergence and Timing-Yield Improvements in Deep Submicrometer Technologies PDF Supporting Paper

Jeng-Liang Tsai, University of Wisconsin - Madison (US)

Track 3: On-chip synthesis and optimization

Behavioral Synthesis of Asynchronous Circuits PDF Supporting Paper

Sune Fallgaard Nielsen, Technical University of Denmark (DK)

Compression-Based Memory Management PDF Supporting Paper

Ozcan Ozturk, Pennsylvania State University (US)

Efficient and Accurate Gate Sizing with Piecewise Convex Models PDF Supporting Paper

Hiran Tennakoon, University of Washington, Seattle (US)

Track 4: System-level synthesis and optimization

PDF Supporting Paper Power- and Temperature-Aware Techniques for Integrated Circuit Runtime Management

Zhijian Lu, University of Virginia (US)

Energy Conservation for Mobile Embedded Systems PDF Supporting Paper

Yongguo Mei, Purdue University (US)

Energy Management for Battery-Powered Reconfigurable Computing Platforms and Networks PDF Supporting Paper

Jawad Khan, University of Cincinnati (US)

Low-Power LCD Display Systems PDF Supporting Paper

Hojun Shim, Seoul National University (KR)

On Instruction-Set Generation for Real-Time Processors PDF Supporting Paper

Gero Dittmann, IBM Research (CH)

Optimization Techniques for Arithmetic Expressions PDF Supporting Paper

Anup Hosangadi, University of California - Santa Barbara (US)

Physical Aware High Level Synthesis for FPGAs PDF Supporting Paper

Renqiu Huang, University of Cincinnati (US)

Power-Thermal Modeling and Management of Integrated Circuits and Systems PDF Supporting Paper

Weiping Liao, University of California - Los Angeles (US)

Soft Errors: Modeling and interactions with power optimizations PDF Supporting Paper

Vijay Degalahal, Penn State (US)

System-level Optimization and Validation for PDF Supporting Paper Power-Constrained Embedded Systems

Jinfeng Liu, University of California - Irvine (US)

Track 5: Testing

Efficient Testing and Test Cost Reduction for MEMS Devices PDF Supporting Paper

Sounil Biswas, Carnegie Mellon University (US)

Solutions for Emerging Problems in Modular System-on-a-Chip Testing PDF Supporting Paper

Qiang Xu, McMaster University (CA)

Testability and Security: Can they work together? PDF Supporting Paper

David Hely, ST Microelectronics (FR)

Track 6: Verification

Abstraction-Guided Symbolic Model Checking PDF Supporting Paper

Kairong Qian, University of New South Wales (AU)

Efficient Algorithm for Finding All Satisfying Assignments PDF Supporting Paper

HoonSang Jin, Univ. of Colorado - Boulder (US)

Functional Equivalence Checking for Verification of Transformations on Array-Intensive Programs PDF Supporting Paper

K.C. Shashidhar, Katholieke Universiteit Leuven (BE)

Track 7: FPGAs, reconfigurable systems

Decomposition in logic synthesis PDF Supporting Paper

Maxim Teslenko, Royal Institute of Technology (SE)

Design of An FPGA-based Computing Platform for Real-time 3D Medical Imaging PDF Supporting Paper

Jianchun Li, Case Western Reserve University (US)

Track 8: Emerging technologies

Automatic design of biofluidic microcircuits PDF Supporting Paper

Anton J. Pfeiffer, Carnegie Mellon University (US)

Synthesis, Testing, and Reconfiguration Techniques for Digital Microfluidic Biochips PDF Supporting Paper

Fei Su, Duke University (US)

Using Hardware Engineering in Quantum Computation: Efficient Circuit Simulation and Reliability Improvement PDF Supporting Paper

Mihai Udrescu, University Politehnica of Timisoara, Romania (RO)

Contact Information

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Last modified April 12, 2005