13th ACM/SIGDA Ph.D. Forum at DAC

Wednesday, June 16th, 2010 
Room 204AB 
Anaheim Convention Center 
Anaheim, CA 

1. Approximate logic circuits: Theory and applications
   Mihir Choudhury, Rice University, USA
2. Yield Enhancement through Pre- and Post-Silicon Adaptation
   Cheng Zhuo, University of Michigan at Ann Arbor, USA
3. Methods and Algorithms for Scalable Verification of Asynchronous Designs
   Haiqiong Yao, University of South Florida, USA
4. Instruction Cache Exploration and Optimization for Embedded Systems
   Yun Liang, National University of Singapore, Singapore
5. Energy Efficient Transactional Memory For Embedded Architectures
   Cesare Ferri, Brown University, USA
6. Efficient SMT Solving for Hardware Model Checking
   Hyondeuk Kim, University of Colorado at Boulder, USA
7. Timing Analysis of Model-driven Embedded Software
   Lei Ju, National University of Singapore, Singapore
8. Architecture and Physical Design for Advanced Networks-on-Chip
   Wooyoung Jang, University of Texas at Austin, USA
9. Robust Prediction and Optimization of Circuit Performance under Process Variations
   Jin Sun, The University of Arizona, USA
10. Low-Cost Quality Assurance Techniques for High-Performance Mixed-Signal/RF Circuits and Systems
    Hsiu-Ming Chang, University of California Santa Barbara, USA
11. Cost-effective Lifetime and Yield Optimization for NoC-based MPSoCs
    Brett Meyer, Carnegie Mellon University, USA
12. Workload Modeling and Characterization in Multicore Design
    Paul Bogdan, Carnegie Mellon University, USA
13. Design Methodologies for Improving Embedded Systems with Hardware Accelerators
    Christian Pilato, Politecnico di Milano, Italy
14. Robust FPGA Design Under Variations
    Akhilesh Kumar, University of Waterloo, Canada
15. Reducing Circuit Soft Error Rate (SER): From Combinational to Sequential Circuits
    Kai-Chiang Wu, Carnegie Mellon University, USA
16. A Formula-Driven Approach for Compiling and Optimizing Hardware Implementations of DSP Transforms
    Peter Milder, Carnegie Mellon University, USA
17. Fault and yield aware on-chip memory design and management
    Hyunjin Lee, University of Pittsburgh, USA
18. A Malleable Hardware Accelerator for Energy-Efficient Adaptive Processor
    Somnath Paul, Case Western Reserve University, USA
19. Energy-Aware Memory Allocation Framework for Embedded Data-Intensive Signal Processing Applications
    Ilie Luican, University of Illinois at Chicago, USA
20. Power Delivery Design and Optimization in 3D Integrated Circuits
    Nauman Khan, Tufts University, USA
21. Application mapping onto coarse-grained reconfigurable architecture
    Ganghee Lee, Seoul National University, Korea
22. Cost and Reliability Modeling of Spare-Enhanced Multi-Core Processors
    Saeed Shamshiri, University of California Santa Barbara, USA
23. Order Reduction of Parameterized Structured EM-based Linear Models
    Jorge Fernandez Villena, INESC ID / IST - T.U. Lisbon, Portugal
24. Efficient Approaches For Functional Validation of SOC Designs Using High-Level Specifications
    Mingsong Chen, University of Florida, USA
25. Architecting Systems for using Emerging Interconnect Technologies
    Soumya Eachempati, Pennsylvania State University, USA
26. Physically-Aware N-Detect Test: Generation and Evaluation
    Yen-Tzu Lin, Carnegie Mellon University, USA
27. Ultra Low-Power and Robust Digital Signal Processing Algorithm and Hardware for Implantable Neural Interface Microsystems
    Seetharam Narasimhan, Case Western Reserve University, USA
28. Reliability Enhancement against Soft Errors in SRAM-based Programmable Systems
    Shahin Golshan, University of California Irvine, USA

Last modified June 3, 2010