The 12th SIGDA Ph.D. Forum at DAC

Tuesday, July 28th, 2010 
Room 134
Moscone Center 
San Francisco, CA 

1. System Design and Automated Synthesis of Complex Mixed-Signal IP Blocks
   Pieter Palmers, K. U. Leuven, Belgium
2. Logic Re-Synthesis for FPGAs by SAT-based Boolean Matching
   Yu Hu, UCLA, USA
3. Runtime Adaptive System-On-Chip Communication Architecture
   Mohammad Abdullah Al Faruque, University of Karlsruhe, Germany
4. RISPP: A Run-time Adaptive Reconfigurable Embedded Processor
   Lars Bauer, University of Karlsruhe, Germany
5. Performance and Reliability Enhancement of Nano-CMOS Designs
   Ashutosh Chakraborty, University of Texas at Austin, USA
6. Wireless Network-On-Chip: A Novel Ultraperformance Communication Paradigm for Gigascale Many-core SoC
   Yi Wang, University of Louisiana at Lafayette, USA
7. Spin-Torque Transfer (STT) MRAM Circuit and System Design
   Wei Xu, Rensselaer Polytechnic Institute, USA
8. Probabilistic Modeling and Optimization for Circuit Reliability
   Natasa Miskov-Zivanov, Carnegie Mellon University, USA
9. Robust Heterogeneous System Design in Spintronics: Error Resilient Spin Torque MRAM (STT MRAM) Design
   Jing Li, Purdue University, USA
10. Towards a Design Flow for Reversible Logic
    Robet Wille, University of Bremen, Germany
11. Network Flow Based Physical Synthesis and Placement Algorithms
    Huan Ren, University of Illinois at Chicago, USA
12. Dependability-Aware Embedded System-Level Design
    Michael Glass, University of Erlangen-Nuremberg, Germany
13. Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
    Aseem Gupta, UC Irvine, USA
14. Design Planning for Chip-Package-Board Co-Design
    Ren-Jie Lee, National Chiao Tung University, Taiwan
15. Design and Optimization Tools for Digital Microfluidic Biochips
    Yang Zhao, Duke University, USA
16. Design Automation and Analysis of Resonant Rotary Clocking Technology at Multi-GHz Range
    Vinayak Honkote, Drexel University, USA
17. Design Automation for Self-Adjusting Architectures
    Jieyi Long, Northwestern University, USA
18. User-Aware Design Methodologies and Optimization Techniques for Embedded Systems-On-Chip
    Chen-Ling Chou, Carnegie Mellon University, USA
19. Uncertainties Modeling and Stochastic Optimization for the Power Integrity of VLSI Circuits and Systems
    Yiyu Shi, UCLA, USA
20. Algorithm/Architecture Co-Design for Low Power and Parametric Robustness Through Adaptive Quality Modulation
    Georgios Karakonstantis, Purdue University, USA
21. The SYS SoC Infrastructure IP's: SoC Enabling Technologies
    Fu-Ching Yang, Sun Yat-sen University, Taiwan
22. Modern VLSI Placement Considering Performance and Reliability
    Zhe-Wei Jiang, National Taiwan University, Taiwan
23. Algorithms for Topology SYnthesis of Analog Circuits
    Angan Das, University of Cincinnati, USA
24. Hardware Protection and Authentication Through Netlist Level Obfuscation
    Rajat Subhra Chakraborty, Case Western Reserve University, USA
25. Low-Power Operation of Integrated Circuits in the Presence of Process Variation
    Amlan Ghosh, University of Utah, USA
26. System Level Design Methodologies for Insturction-Set Extensible Processors
    Huynh Phung Huynh, National University of Singapore, Singapore
27. High-Performance Architectures for Brain Circuit Simulation
    Jayram Moorkanikara Nageswaran, UC Irvine, USA