DATE 2003 Table of Contents

<BODY> <H3><A HREF="../../../../../main_ss.htm">Main Page</A></BR> DATE 2003 : [ <A HREF="dfabs.htm">Abstracts</A> ] [ <A HREF="dfsess.htm">Session Index</A> ] [ <A HREF="dfai.htm">Author Index</A> ]</H3> <HR> <H2>DATE 2003 TABLE OF CONTENTS - DESIGNERS' FORUM</H2> <B> Sessions: [<A HREF="#sess1d">1D</A>] [<A HREF="#sess1e">1E</A>] [<A HREF="#sess2d">2D</A>] [<A HREF="#sess3d">3D</A>] [<A HREF="#sess3e">3E</A>] [<A HREF="#sess4d">4D</A>] [<A HREF="#sess5d">5D</A>] [<A HREF="#sess6d">6D</A>] [<A HREF="#sess7d">7D</A>]<P> <A HREF="../../df_files/forumcom.pdf">Designers' Forum Committee</A><BR> <A HREF="../../df_files/softcom.pdf">Embedded Software Forum Committee</A><BR> <A HREF="../../pdffiles/cfp.pdf">Call for Papers DATE 2004</A><P> </B> <HR> <H2>1D:<A HREF="dfabs.htm#sess1d" NAME="sess1d"> Design Case Studies </A></H2> <I> Moderators: C. Das, IMEC, BE; K. Torki, CMP, FR </I><P> <DL> <DT> <A HREF="dfabs.htm#01d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2] <DD><I> H. Iwasaki, J. Naganuma, K. Nitta, K. Nakamura, T. Yoshitome, M. Ogura, Y. Nakajima, Y. Tashiro, T. Onishi, M. Ikeda, and M. Endo </I><P> <DT> <A HREF="dfabs.htm#01d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8] <DD><I> H. Stolberg, M. Berekovic, L. Friebe, S. Moch, S. FlŸgel, X. Mao, M. Kulaczewski, H. Klu§mann, and P. Pirsch </I><P> <DT> <A HREF="dfabs.htm#01d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14] <DD><I> G. Lykakis, N. Mouratidis, G. Konstantoulakis, K. Vlachos, N. Nikolaou, S. Perissakis, G. Sourdis, D. Pnevmatikatos, and D. Reisis </I><P> <DT> <A HREF="dfabs.htm#01d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20] <DD><I> A. Panato, M. Barcelos, and R. Reis </I><P> <DT> <A HREF="dfabs.htm#01d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26] <DD><I> M. Caldari, M. Conti, L. Pieralisi, C. Turchetti, M. Coppola, and S. Curaba </I><P> <DT> <A HREF="dfabs.htm#01d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32] <DD><I> M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti </I><P> </DL> <HR> <H2>1E:<A HREF="dfabs.htm#sess1e" NAME="sess1e"> Embedded Operating Systems for SoC (Embedded Software Forum) </A></H2> <I> Moderators: S. Vassiliadis, TU Delft, NL; R. Ernst, TU Braunschweig, DE </I><P> <DL> <DT> <A HREF="dfabs.htm#01e_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Designing System-Level Software Solutions for Open OSâs on 3g Wireless Handsets [p. 40] <DD><I> S. Glaeson and E. Petit </I><P> <DT> <A HREF="dfabs.htm#01e_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study [p. 41] <DD><I> M. Besana and M. Borgatti </I><P> <DT> <A HREF="dfabs.htm#01e_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Formal Methods for Integration of Automotive Software [p. 45] <DD><I> M. Jersak, K. Richter, R. Ernst, J. Braam, Z. Jiang, and F. Wolf </I><P> <DT> <A HREF="dfabs.htm#01e_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect [p. 51] <DD><I> F. PŽtrot and P. Gomez </I><P> <DT> <A HREF="dfabs.htm#01e_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/01e_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results [p. 57] <DD><I> B. Nicolescu and R. Velazco </I><P> </DL> <HR> <H2>2D:<A HREF="dfabs.htm#sess2d" NAME="sess2d"> Hot Topic: Network Processing Key Technologies and Architectural Components </A></H2> <I> Organizer/Moderator: P. Paulin, STMicroelectronics, FR </I><P> <DL> <DT> <A HREF="dfabs.htm#02d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/02d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Network Processing Challenges and an Experimental NPU Platform [p. 64] <DD><I> P. Paulin, C. Pilkington, and E. Bensoudane </I><P> <DT> <A HREF="dfabs.htm#02d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/02d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70] <DD><I> A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. Zeferino </I><P> <DT> <A HREF="dfabs.htm#02d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/02d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> NPSE: A High-Performance Network Packet Search Engine [p. 74] <DD><I> N. Soni, N. Richardson, L. Huang, S. Rajgopal, and G. Vlantis </I><P> </DL> <HR> <H2>3D:<A HREF="dfabs.htm#sess3d" NAME="sess3d"> SystemC Based Design </A></H2> <I> Moderators: F. Fummi, Verona U, IT; A. Braun, Tuebingen U, DE </I><P> <DL> <DT> <A HREF="dfabs.htm#03d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Proposal for Transaction-Level Verification with Component Wrapper Language [p. 82] <DD><I> K. Ara and K. Suzuki </I><P> <DT> <A HREF="dfabs.htm#03d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88] <DD><I> F. Carbognani, C. Ip, P. Bates, A. Cochrane, and C. Lennard </I><P> <DT> <A HREF="dfabs.htm#03d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95] <DD><I> A. Sayinta, G. Canverdi, A. Alshawa, M. Pauwels, and W. Dehaene </I><P> <DT> <A HREF="dfabs.htm#03d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> SystemC-VHDL Co-Simulation and Synthesis in the HW Domain [p. 101] <DD><I> M. Bombana and F. Bruschi </I><P> <DT> <A HREF="dfabs.htm#03d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106] <DD><I> M. Coppola, S. Curaba, G. Maruccia, and M. Grammatikakis </I><P> <DT> <A HREF="dfabs.htm#03d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Synthesis of Complex Control Structures from Behavioral SystemC Models [p. 112] <DD><I> F. Bruschi and F. Ferrandi </I><P> </DL> <HR> <H2>3E:<A HREF="dfabs.htm#sess3e" NAME="sess3e"> Embedded Software Design and Implementation (Embedded Software Forum) </A></H2> <I> Moderators: P. Kajfasz, Thales, FR; M. Coppola, STMicroelectronics, FR </I><P> <DL> <DT> <A HREF="dfabs.htm#03e_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120] <DD><I> I. Moussa, T. Grellier, and G. Nugyen </I><P> <DT> <A HREF="dfabs.htm#03e_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices [p. 126] <DD><I> M. Gštze </I><P> <DT> <A HREF="dfabs.htm#03e_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132] <DD><I> Y. Cho, G. Lee, K. Choi, S. Yoo, N. Zergainoh </I><P> <DT> <A HREF="dfabs.htm#03e_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device [p. 138] <DD><I> S. Honda and H. Takada </I><P> <DT> <A HREF="dfabs.htm#03e_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144] <DD><I> H. Du, N. Tabrizi, N. Bagherzadeh, M. Sanchez-Elez, M. Fernandez, and M. Anido </I><P> <DT> <A HREF="dfabs.htm#03e_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/03e_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development [p. 150] <DD><I> S. Jan, P. de Dios, and S. Edwards </I><P> </DL> <HR> <H2>4D:<A HREF="dfabs.htm#sess4d" NAME="sess4d"> Design Exploration Methodologies </A></H2> <I> Moderators: M. Bombana, Siemens ICN, IT; F. Ghenassia, STMicroelectronics, FR </I><P> <DL> <DT> <A HREF="dfabs.htm#04d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158] <DD><I> D. Truscan, S. Virtanen, and J. Lilius </I><P> <DT> <A HREF="dfabs.htm#04d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems [p. 164] <DD><I> S. Brini, D. Benjelloun, and F. Castanier </I><P> <DT> <A HREF="dfabs.htm#04d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170] <DD><I> S. Kodase, S. Wang, and K. Shin </I><P> <DT> <A HREF="dfabs.htm#04d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176] <DD><I> O. Ogawa, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, Y. Takai, S. de Noyer, and P. Chauvet </I><P> <DT> <A HREF="dfabs.htm#04d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182] <DD><I> G. Palermo, C. Silvano, and V. Zaccaria </I><P> <DT> <A HREF="dfabs.htm#04d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/04d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188] <DD><I> N. Drago, F. Fummi, M. Poncino, M. Monguzzi, and G. Perbellini </I><P> </DL> <HR> <H2>5D:<A HREF="dfabs.htm#sess5d" NAME="sess5d"> Design Methodologies </A></H2> <I> Moderators: V. Gerousis, Infineon, DE; E. Stoy, Ericsson, SE </I><P> <DL> <DT> <A HREF="dfabs.htm#05d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Defining Cost Functions for Robust IC Design and Optimization [p. 196] <DD><I> ç. BŸrmen, J. Puhan, and T. Tuma </I><P> <DT> <A HREF="dfabs.htm#05d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> SoC Design and Test Considerations [p. 202] <DD><I> M. Schrader and R. McConnell </I><P> <DT> <A HREF="dfabs.htm#05d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A System to Validate and Certify Soft and Hard IP [p. 208] <DD><I> B. Laurent and T. Karger </I><P> <DT> <A HREF="dfabs.htm#05d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214] <DD><I> M. Caldari, M. Conti, P. Crippa, G. Marozzi, F. Di Gennaro, S. Orcioni, and C. Turchetti </I><P> <DT> <A HREF="dfabs.htm#05d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Set Top Box SoC Design Methodology at STMicroelectronics [p. 220] <DD><I> F. Remond and P. Bricaud </I><P> <DT> <A HREF="dfabs.htm#05d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/05d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Verification of a Complex SoC: The PRO<SUP>3</SUP> Case-Study [p. 224] <DD><I> F. Andritsopoulos, G. Doumenis, C. Charopoulos, F. Karoubalis, Y. Mitsos, F. Petreas, I. Theologitou, S. Perissakis, and D. Reisis </I><P> </DL> <HR> <H2>6D:<A HREF="dfabs.htm#sess6d" NAME="sess6d"> System Level Design Case Studies </A></H2> <I> Moderators: A. Reutter, Robert Bosch GmbH, DE; M. Poncino, Verona U, IT </I><P> <DL> <DT> <A HREF="dfabs.htm#06d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232] <DD><I> L. Mangeruca, A. Ferrari, A. Sangiovanni-Vincentelli, M. Pennese, and A. Pierantoni </I><P> <DT> <A HREF="dfabs.htm#06d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238] <DD><I> M. Verderber, A. Zemva, and D. Lampret </I><P> <DT> <A HREF="dfabs.htm#06d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Reconfigurable Signal Processing in Wireless Terminals [p. 244] <DD><I> S. Di Matteo, S. Rossi, R. Bonitz, E. SchŸler, P. Rao, and J. Helmschmidt </I><P> <DT> <A HREF="dfabs.htm#06d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250] <DD><I> A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, and E. Martin </I><P> <DT> <A HREF="dfabs.htm#06d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256] <DD><I> C. Sauer, M. Gries, C. Kulkarni, and K. Keutzer </I><P> <DT> <A HREF="dfabs.htm#06d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/06d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Solution for Hardware Emulation of Non Volatile Memory Macrocells [p. 262] <DD><I> A. Pirola </I><P> </DL> <HR> <H2>7D:<A HREF="dfabs.htm#sess7d" NAME="sess7d"> Analogue and Mixed Signal Methodology Design </A></H2> <I> Moderators: L. Torres, LIRMM, FR; J.M. Portal, Marseille Polytech U, FR </I><P> <DL> <DT> <A HREF="dfabs.htm#07d_1"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Bluetooth Transceiver Design with VHDL-AMS [p. 268] <DD><I> R. Ahola, D. Wallner, and M. Sida </I><P> <DT> <A HREF="dfabs.htm#07d_2"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies [p. 274] <DD><I> P. Daglio and C. Roma </I><P> <DT> <A HREF="dfabs.htm#07d_3"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280] <DD><I> A. Mounir, A. Mostafa, and M. Fikry </I><P> <DT> <A HREF="dfabs.htm#07d_4"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286] <DD><I> U. Knšchel, T. Markwirth, R. Kakerow, R. Atukula, and J. Hartung </I><P> <DT> <A HREF="dfabs.htm#07d_5"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292] <DD><I> M. McCorquodale, F. Gebara, K. Kraver, E. Marsman, R. Senger, and R. Brown </I><P> <DT> <A HREF="dfabs.htm#07d_6"><IMG SRC="../../../../../icons/absicon.gif"></A> <A HREF="../../df_files/07d_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A> Synthesis of CMOS Analog Cells Using AMIGO [p. 297] <DD><I> R. Iskander, M. Aly, M. Magdy, N. Hassan, N. Soliman, S. Moussa, and M. Dessouky </I><P> </DL>