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DATE 2003 :
[ <A HREF="dftoc.htm">Table of Contents</A> ]
[ <A HREF="dfsess.htm">Session Index</A> ]
[ <A HREF="dfai.htm">Author Index</A> ]</H3>
<HR>
<H2>DATE 2003 ABSTRACTS - DESIGNERS' FORUM</H2>
<B>
Sessions:
[<A HREF="#sess1d">1D</A>]
[<A HREF="#sess1e">1E</A>]
[<A HREF="#sess2d">2D</A>]
[<A HREF="#sess3d">3D</A>]
[<A HREF="#sess3e">3E</A>]
[<A HREF="#sess4d">4D</A>]
[<A HREF="#sess5d">5D</A>]
[<A HREF="#sess6d">6D</A>]
[<A HREF="#sess7d">7D</A>]<P>
</B>
<HR>
<H2>1D:<A NAME="sess1d">
Design Case Studies
</A></H2>
<I>
Moderators: C. Das, IMEC, BE; K. Torki, CMP, FR
</I><P>
<DL>
<DT>
<A HREF="../../df_files/01d_1.pdf" NAME="01d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for
Large Scale Processing beyond HDTV Level [p. 2]
<DD><I>
H. Iwasaki, J. Naganuma, K. Nitta, K. Nakamura, T. Yoshitome, M. Ogura,
Y. Nakajima, Y. Tashiro, T. Onishi, M. Ikeda, and M. Endo
</I><P>
This paper proposes a new architecture for VASA, a
single-chip MPEG-2 422P@HL CODEC LSI with multichip
configuration for large scale processing beyond the
HDTV level, and demonstrates its flexibility and usefulness.
This architecture consists of triple encoding cores,
a decoding core, a multiplexer/de-multiplexer core, and
several dedicated application-specific hardware modules
with a hierarchical flexible communication scheme for high-performance
data transfer. VASA is the world's first single-chip
full-specs MPEG-2 422P@HL CODEC LSI with a
multi-chip configuration. The VASA implements MPEG-2
video and system CODEC with generic audio CODEC interfaces.
An LSI incorporating the architecture was successfully
fabricated using the 0.13-µm eight-metal CMOS
process. The architecture not only provides an MPEG-2
422P@HL CODEC but also large scale processing beyond
the HDTV level for digital cinema and multi-view/-angled
live TV applications with a multi-chip configuration. The
VASA implementations will lead to a new dimension in future
high-quality, high-resolution digital multimedia entertainment.<P>
<DT>
<A HREF="../../df_files/01d_2.pdf" NAME="01d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
<DD><I>
H. Stolberg, M. Berekovic, L. Friebe, S. Moch, S. Flgel, X. Mao,
M. Kulaczewski, H. Klu§mann, and P. Pirsch
</I><P>
The HiBRID-SoC multi-core system-on-chip targets a
wide range of application fields with particularly high
processing demands, including general signal processing
applications, video and audio de-/encoding, and a combination
of these tasks. For this purpose, the HiBRID-SoC
integrates three fully programmable processors cores and
various interfaces onto a single chip, all tied to a 64-Bit
AMBA AHB bus. The processor cores are individually optimized
to the particular computational characteristics of different
application fields, complementing each other to deliver
high performance levels with high flexibility at reduced
system cost. The HiBRID-SoC is fabricated in a 0.18 µm
6LM standard-cell technology, occupies about 82 mm2, and
operates at 145 MHz.<P>
<DT>
<A HREF="../../df_files/01d_3.pdf" NAME="01d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
<DD><I>
G. Lykakis, N. Mouratidis, G. Konstantoulakis, K. Vlachos,
N. Nikolaou, S. Perissakis, G. Sourdis, D. Pnevmatikatos, and D. Reisis
</I><P>
We present an innovative protocol processor component
that combines wire-speed processing for low-level,
and best effort processing for higher-level protocols. The
component is a System-on-Chip that integrates variable
size packet buffering, specialised cores for header and
field processing, generic RISC cores and scheduling
blocks. We focus on the main innovation, the reprogrammable
pipeline module, and discuss its internal architecture,
optimised to perform field processing on byte
streams, as well as protocol processing on complex data
structures. Furthermore, we present how modern and new
tools were used in system dimensioning, design, and verification
phases. The chip is able to handle up to 512K
flows organised in individual queues. It embeds 5 custom
cores optimised for field processing, 3 typical RISC cores
for packet processing and 11 generic and application
specific hardware blocks. Itās been prototyped in UMC
0.18uCMOS technology in a 1096-pin BGA package and
operates at 200MHz for 2.5Gbps links.<P>
<DT>
<A HREF="../../df_files/01d_4.pdf" NAME="01d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20]
<DD><I>
A. Panato, M. Barcelos, and R. Reis
</I><P>
This work presents a soft IP description of Rijndael,
the Advanced Encryption Standard (AES) of National
Institute of Standards and Technology (NIST). This
Rijndael implementation run its symmetric cipher
algorithm using a key size of 128 bits, mode called
AES128. The focus here is to produce a low area IP
achieving good performance. To do that, we propose a
architecture using mixed bit size processing. The usage of
memory has a significant decrease. The same
methodology is used to implement three versions: the first
one only encrypts the data, the second one decrypts and
the third one performs both operation at same device. The
implementation choice was Acex1K and Cyclone devices
of Altera. The paper presents a introduction of
cryptography, the AES contest that defined Rijndael as
the new standard, the AES-128 structure and some
results, such as device occupation, clock frequency,
throughput and latency.<P>
<DT>
<A HREF="../../df_files/01d_5.pdf" NAME="01d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
<DD><I>
M. Caldari, M. Conti, L. Pieralisi, C. Turchetti, M. Coppola, and S. Curaba
</I><P>
The concept of a SOC platform architecture introduces
the concept of a communication infrastructure. In the
transaction-level a finite set of architecture components
(memories, arithmetic units, address generators, caches,
etc) communicate among each other over shared
resources (buses). Until recently, modeling architectures
required pin-level hardware descriptions, typically coded
in RTL. Great effort is required to design and verify the
models, and simulation at this level of detail is tediously
slow. Transaction level modeling is the solution.
Transaction level models (TLMs) effectively create an
executable platform model that simulates orders of
magnitude faster than a RTL model.
In this paper, we present a SystemC 2.0 TLM of the
AMBA architecture developed by ARM, oriented to SOC
platform architectures.<P>
<DT>
<A HREF="../../df_files/01d_6.pdf" NAME="01d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
<DD><I>
M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti
</I><P>
The specification on power consumption of a digital
system is extremely important due to the growing
relevance of the market of portable devices and must be
taken into account since the early phases of a complex
System-on-Chip design.
In this paper some guidelines are provided for the
integration of the information on power consumption in
the executable model of parameterized cores, with
particular attention to the AMBA AHB bus. This will give
important information for the analysis and choice between
different design architectures driven by functional, timing
and power constraints of the System-on-Chip.<P>
</DL>
<HR>
<H2>1E:<A NAME="sess1e">
Embedded Operating Systems for SoC (Embedded Software Forum)
</A></H2>
<I>
Moderators: S. Vassiliadis, TU Delft, NL; R. Ernst, TU Braunschweig, DE
</I><P>
<DL>
<DT>
<A HREF="../../df_files/01e_1.pdf" NAME="01e_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Designing System-Level Software Solutions for Open OSās on 3g Wireless Handsets [p. 40]
<DD><I>
S. Glaeson and E. Petit
</I><P>
<DT>
<A HREF="../../df_files/01e_2.pdf" NAME="01e_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS:
A Design Case Study [p. 41]
<DD><I>
M. Besana and M. Borgatti
</I><P>
Consistency, accuracy and efficiency are key aspects for
practical usability of a system design flow featuring
automatic code generation. Consistency is the property of
maintaining the same behaviour at different levels of
abstraction through synthesis and refinement, leading to
functionally correct implementation. Accuracy is the
property of having a good estimation of system
performances while evaluating a high-level representation
of the system. Efficiency is the property of introducing low
overheads and preserving performances at the
implementation level.
RTOS is a key element of the link to implementation flow.
In this paper we capture relevant high-level RTOS
parameters that allow consistency, accuracy and
efficiency to be verified in a top-down approach. Results
from performance estimation are compared against
measurements on the actual implementation.
Experimental results on automatically generated code
show design flow consistency, an accuracy error of about
0.66% and an overhead of about 11.8% in term of speed.<P>
<DT>
<A HREF="../../df_files/01e_3.pdf" NAME="01e_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Formal Methods for Integration of Automotive Software [p. 45]
<DD><I>
M. Jersak, K. Richter, R. Ernst, J. Braam, Z. Jiang, and F. Wolf
</I><P>
Novel functionality, configurability and higher efficiency
in automotive systems require sophisticated embedded software,
as well as distributed software development between
manufacturers and control unit suppliers. However, at least
for engine control units, there exists today no well-defined
software integration process that satisfies all key requirements
of automotive manufacturers.
We propose a methodology for safe integration of automotive
software functions where required performance information
is exchanged while each partnerās IP is protected.
We claim that in principle performance requirements and
constraints (timing, memory consumption) for each software
component and for the complete ECU can be formally
validated, and believe that ultimately such formal analysis
will be required for legal certification of an ECU.<P>
<DT>
<A HREF="../../df_files/01e_4.pdf" NAME="01e_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS
Multiprocessor with VCI Interconnect [p. 51]
<DD><I>
F. Ptrot and P. Gomez
</I><P>
This paper relates our experience in designing from
scratch a multi-threaded kernel for a MIPS R3000 on-chip
multiprocessor. We briefly present the target architecture
build around a VCI compliant interconnect, and the CPU
characteristics. Then we focus on the implementation of
part of the POSIX 1003.1b and 1003.1c standards. We conclude
this case study by simulation results obtained by cycle
true simulation of an MJPEG video decoder application on
the multiprocessor, using several scheduler organizations
and architectural parameters.<P>
<DT>
<A HREF="../../df_files/01e_5.pdf" NAME="01e_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results [p. 57]
<DD><I>
B. Nicolescu and R. Velazco
</I><P>
In this paper is described a software technique allowing
to detect soft errors occurring in processor-based digital
architectures. The detection mechanism is based on a set of
rules allowing the transformation of the target application
into a new one, having same functionalities but being able
to identify bit-flips arising in memory areas as well as those
perturbing the processorās internal registers. Experimental
results issued from fault injection sessions and preliminary
radiation test campaigns performed in complex DSP
processor, provide objective figures about the efficiency of
the proposed error detection technique.<P>
</DL>
<HR>
<H2>2D:<A NAME="sess2d">
Hot Topic: Network Processing Key Technologies and Architectural Components
</A></H2>
<I>
Organizer/Moderator: P. Paulin, STMicroelectronics, FR
</I><P>
<DL>
<DT>
<A HREF="../../df_files/02d_1.pdf" NAME="02d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Network Processing Challenges and an Experimental NPU Platform [p. 64]
<DD><I>
P. Paulin, C. Pilkington, and E. Bensoudane
</I><P>
The fast-changing communications market requires
high-performance yet flexible network -processing
platforms. StepNPTM is an exploratory network processor
simulation environment for exploring router applications,
multiprocessor network-processing architectures, and SoC
tools. Supporting model interaction, instrumentation, and
analysis, the platform lets R&D teams easily add new
processors, coprocessors, and interconnects.<P>
<DT>
<A HREF="../../df_files/02d_2.pdf" NAME="02d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
<DD><I>
A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. Zeferino
</I><P>
This paper presents the SPIN micro-network that is a
generic, scalable interconnect architecture for system on
chip. The SPIN architecture relies on packet switching
and point-to-point bi-directional links between the routers
implementing the micro-network. SPIN gives the system
designer the simple view of a single shared address space
and provides a variable number of VCI compliant
communication interfaces for both initiators (masters) and
targets (slaves). Performance comparisons between a
classical PI-bus based interconnect and the SPIN micronetwork
are analyzed.<BR>
Keywords<BR>
Systems -on-Chip. Networks-on-Chip. Embedded Systems.<P>
<DT>
<A HREF="../../df_files/02d_3.pdf" NAME="02d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
NPSE: A High-Performance Network Packet Search Engine [p. 74]
<DD><I>
N. Soni, N. Richardson, L. Huang, S. Rajgopal, and G. Vlantis
</I><P>
This paper describes the NPSE, a high-performance
SRAM-based network packet search engine which has
the primary application of supporting IPv4 and IPv6
forwarding. It is based on a high-speed hardware
implementation of a tree-based storage and retrieval
algorithm, which is memory and power-efficient
compared to traditional CAM-based look-up methods.<P>
</DL>
<HR>
<H2>3D:<A NAME="sess3d">
SystemC Based Design
</A></H2>
<I>
Moderators: F. Fummi, Verona U, IT; A. Braun, Tuebingen U, DE
</I><P>
<DL>
<DT>
<A HREF="../../df_files/03d_1.pdf" NAME="03d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Proposal for Transaction-Level Verification with Component Wrapper Language [p. 82]
<DD><I>
K. Ara and K. Suzuki
</I><P>
We propose a new approach to accelerate transaction
level verification by raising the productivity of the
verification suites including test patterns, protocol
checker, and simulation-coverage analyzer. This
approach combines the conventional transaction level
language such as C and the signal level language based
on our previously developed Component Wrapper
Language (CWL).
This approach is based on two concepts. The first one
is a complete separation between transaction-level
verification and signal-level verification for generating
suitable verification suites in each design phase. The
second one is the quick generation of signal-level
verification suites from the original specification written
in CWL. Experimental results show that our approach
should yield much shorter verification periods versus
conventional methods.<P>
<DT>
<A HREF="../../df_files/03d_2.pdf" NAME="03d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
<DD><I>
F. Carbognani, C. Ip, P. Bates, A. Cochrane, and C. Lennard
</I><P>
The increasing complexity of Systems on Chip (SoC) has
introduced the need for abstract executable specifications
(models) covering both hardware and embedded software.
The new capabilities of SystemC 2.0, such as those added
for transaction-based communication and test-bench
Specification and monitoring, facilitate this SoC modeling.
However, an obstacle to the adoption of abstract modeling
as standard design practice is the lack of well establishes
methodologies for the assessment of model precision. We
describe such a methodology based on the SystemC
Verification Standard implemented by Cadence's
TestBuilder-SC. This methodology enables comparison of
high-level (transaction level) SoC models in SystemC
against implementation RTL models.
An application of the methodology is presented, based on
the AMBA Class Library (ACL) for SystemC being
developed by ARM in collaboration with EDA partners.
The key elements of the methodology are:<BR>
1. A completely reusable testbench that can be used
for simulation and verification of the design at
both high-level (transaction level) of abstraction
and RTL implementation level.<BR>
2. A single database format is used so that data
collected from simulations at each level can easily
be processed and compared
We present an example of effective validation of ARM
PrimeXsys-platform IP components against their RTL
implementation.<P>
<DT>
<A HREF="../../df_files/03d_3.pdf" NAME="03d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
<DD><I>
A. Sayinta, G. Canverdi, A. Alshawa, M. Pauwels, and W. Dehaene
</I><P>
This paper focuses on co-simulation scenarios and their
applications as a part of a system-on-chip (SoC) modeling
and design methodology developed at Alcatel
Microelectronics (now part of STMicroelectronics) within
a wireless local area network (LAN) SoC project. This
methodology proposes to build a SystemC-based
executable model of the system to maintain a bridge
between the algorithmic and the implementation worlds.
The model is used in later phases by means of cosimulation
of SystemC, HDL and firmware. SystemC-HDL
co-simulation scenario provides a way of checking interoperability
of a single designed HW module with the
SystemC model. The SystemC-Instruction Set Simulator
(ISS) co-simulation provides a platform to develop and
verify the firmware that will run on the selected processor
core even before the HW modules are designed. It will be
shown that, with sufficient tool support, these design
stages reduce the complexity of the SoC design and
improve the debugging capabilities.<P>
<DT>
<A HREF="../../df_files/03d_4.pdf" NAME="03d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain [p. 101]
<DD><I>
M. Bombana and F. Bruschi
</I><P>
Embedded systems design requires the development of
complex HW modules to cope with the most stringent
timing constraints of the specifications. This implies
the need to update and enrich HW design
methodologies to face abstraction and novel
requirements. Here we will present some results of
design practice of HW modules in this context. Cosimulation
and synthesis are combined in this
approach to achieve higher abstraction levels in the
design, to improve validation and re-use of previous
designs and human experience. The proposed
methodology is embedded in a SystemC based design
flow. The SystemC-VHDL co-simulator tool is also
based on a SystemC/C++ front-end developed to
support the co-simulation between VHDL and
SystemC. The prototypal state of the adopted tools
increase the novelty and interest of the approach.<P>
<DT>
<A HREF="../../df_files/03d_5.pdf" NAME="03d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]
<DD><I>
M. Coppola, S. Curaba, G. Maruccia, and M. Grammatikakis
</I><P>
Refinement is a key methodology for SoC design. The
proposed IPSIM design environment, based on a C++
modeling library developed on top of SystemC 3.0,
supports an object-oriented design methodology,
separates IP modules into behavior and communication
components and further establishes two inter-module
communication layers. The Message Box layer includes
generic and system-specific communication, while the
driver layer implements higher level user-defined
communications as illustrated in a design example.<P>
<DT>
<A HREF="../../df_files/03d_6.pdf" NAME="03d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Synthesis of Complex Control Structures from Behavioral SystemC Models [p. 112]
<DD><I>
F. Bruschi and F. Ferrandi
</I><P>
In this paper we present the results of a set of experiments
we conducted in order to evaluate the viability of the
behavioral synthesis, relying on the tools available at the
moment in EDA market. To accomplish this we modelled
a complex PCI bus interface in SystemC using a behavioral
style of description. Then we tried to synthesize it by
means of the Synopsis CoCentric SystemC Compiler tool.
The problems arisen during synthesis, in particular those
concerned with the cycle-accurate timing behavior of the
synthesized circuit, were addressed. After analyzing them,
possible solutions were proposed, were possible. Finally, a
summary of the pros and cons of the behavioral synthesis in
SystemC is presented.<P>
</DL>
<HR>
<H2>3E:<A NAME="sess3e">
Embedded Software Design and Implementation (Embedded Software Forum)
</A></H2>
<I>
Moderators: P. Kajfasz, Thales, FR; M. Coppola, STMicroelectronics, FR
</I><P>
<DL>
<DT>
<A HREF="../../df_files/03e_1.pdf" NAME="03e_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120]
<DD><I>
I. Moussa, T. Grellier, and G. Nugyen
</I><P>
This paper presents VISTA, a new methodology and
tool dedicated to analyse system level performance by
executing full-scale SW application code on a
transaction-level model of the SoC platform. The SoC
provider provides a cycle-accurate functional model of
the SoC architecture using the basic SystemC
Transaction Level Modeling (TLM) components
provided by VISTA : bus models, memories, IPs, CPUs,
and RTOS generic services. These components have
been carefully designed to be integrated into a SoC
design flow with an implementation path for automatic
generation of IP HW interfaces and SW device drivers.
The application developer can then integrate the
application code onto the SoC architecture as a set of
SystemC modules. VISTA supports cross-compilation on
the target processor and back annotation, therefore
bypassing the use of an ISS. We illustrate the features
of VISTA through the design and simulation of an
MPEG video decoder application.<P>
<DT>
<A HREF="../../df_files/03e_2.pdf" NAME="03e_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices [p. 126]
<DD><I>
M. Gtze
</I><P>
This paper describes the design considerations of and
preliminary conclusions drawn from an ongoing project
dealing with the design of a software architecture for a
family of so-called smart wireless communication devices
(SWCDs). More specifically, based on an existing hardware
platform, the software architecture is being modeled
using UML in conjunction with suitable framework and
product line modeling approaches to achieve a high degree
of flexibility with respect to variability at both the hardware
and application software end of the spectrum. To this effect,
the design is split into a middleware framework encapsulating
specifics of the underlying hardware platform and
OS, and product line modeling of a comprehensive, versatile
application on top of it.<P>
<DT>
<A HREF="../../df_files/03e_3.pdf" NAME="03e_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]
<DD><I>
Y. Cho, G. Lee, K. Choi, S. Yoo, N. Zergainoh
</I><P>
On-chip communication design includes designing
software (SW) parts (operating system, device drivers, interrupt
service routines, etc.) as well as hardware (HW) parts (on-chip
communication network, communication interfaces of
processor/IP/memory, on-chip memory, etc.). For an efficient
exploration of its design space, we need fast scheduling and
timing analysis. In this work, we tackle two problems (one for
SW and the other for HW) in on-chip communication design.
One is to incorporate the dynamic behavior of SW (interrupt
processing and context switching) into on-chip communication
scheduling. The other is to reduce on-chip data storage
required for on-chip communication, by sharing physical
communication buffers with different communication
transactions. To solve the problems, we present both ILP
(integer linear programming) formulation and heuristic
algorithm, which enable the designer to perform efficient on-chip
communication scheduling and obtain accurate timing
information. Experimental results show the effectiveness of our
work.<P>
<DT>
<A HREF="../../df_files/03e_4.pdf" NAME="03e_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device [p. 138]
<DD><I>
S. Honda and H. Takada
</I><P>
We are investigating an integrated design method for a
device driver and a device in order to efficiently develop
device drivers used in embedded systems. This paper evaluates
whether SpecC, which is proposed as a system level
description language, is applicable to integrated description
language for the integrated design method. We use an
SIO system to confirm the feasibility of using SpecC for integrating
a device and description device driver. We manually
convert the SpecC description to the device, the device
driver and the interface in between and confirm that
the conversion can be automated. We also confirm the feasibility
of conversion when the partition point between the
software and the hardware is changed. As a result, we show
that SpecC could apply as a integrated design language of
the design method.<P>
<DT>
<A HREF="../../df_files/03e_5.pdf" NAME="03e_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
<DD><I>
H. Du, N. Tabrizi, N. Bagherzadeh, M. Sanchez-Elez, M. Fernandez, and M. Anido
</I><P>
MorphoSys is a reconfigurable SIMD architecture. In this
paper, a BSP-based ray tracing is gracefully mapped onto
MorphoSys. The mapping highly exploits ray-tracing
parallelism. A straightforward mechanism is used to
handle irregularity among parallel rays in BSP. To support
this mechanism, a special data structure is established, in
which no intermediate data has to be saved. Moreover,
optimizations such as object reordering and merging are
facilitated. Data starvation is avoided by overlapping data
transfer with intensive computation so that applications
with different complexity can be managed efficiently. Since
MorphoSys is small in size and power efficient, we
demonstrate that MorphoSys is an economic platform for
3D animation applications on portable devices.<P>
<DT>
<A HREF="../../df_files/03e_6.pdf" NAME="03e_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Porting a Network Cryptographic Service to the RMC2000: A Case Study in
Embedded Software Development [p. 150]
<DD><I>
S. Jan, P. de Dios, and S. Edwards
</I><P>
This paper describes our experience porting a transport-layer
cryptography service to an embedded microcontroller.
We describe some key development issues and techniques
involved in porting networked software to a connected, limited
resource device such as the Rabbit RMC2000 we chose
for this case study. We examine the effectiveness of a few
proposed porting strategies by examining important program
and run-time characteristics.<P>
</DL>
<HR>
<H2>4D:<A NAME="sess4d">
Design Exploration Methodologies
</A></H2>
<I>
Moderators: M. Bombana, Siemens ICN, IT; F. Ghenassia, STMicroelectronics, FR
</I><P>
<DL>
<DT>
<A HREF="../../df_files/04d_1.pdf" NAME="04d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158]
<DD><I>
D. Truscan, S. Virtanen, and J. Lilius
</I><P>
In this paper we present a design case study in configuring
our protocol processor architecture to meet the performance
requirements of IPv6 routing at gigabit speeds. Our
methodology makes it possible to make fast reliable analyses
of the problem on a high level and to find its key bottlenecks
and design constraints. Based on the analyses we
suggest architectural configurations for the target application.
The best configurations can then be further analyzed
in more detailed system-level simulations and physical estimations.<P>
<DT>
<A HREF="../../df_files/04d_2.pdf" NAME="04d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Flexible Virtual Platform for Computational and Communication Architecture
Exploration of DMT VDSL Modems [p. 164]
<DD><I>
S. Brini, D. Benjelloun, and F. Castanier
</I><P>
In this paper a high-level SoC architecture exploration
of DMT (Discrete Multitone) VDSL transceivers (Very
high speed Digital Subscriber Line) is presented. A
flexible and complete virtual platform was developed for
the purpose, exploiting the paradigm of ćorthogonalization
of concernsä (functionality independent from
architecture) in the framework of Cadence VCC system
level design tool. An accurate processor model, obtained
through the back-annotation of profiling results on a
target DSP core, allowed the exploration of different
HW/SW partitioning and the study of the computational
units required. A transaction-accurate VCC bus model
was developed for the investigation of the on-chip bus
architecture and its relevant parameters dimensioning.<P>
<DT>
<A HREF="../../df_files/04d_3.pdf" NAME="04d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170]
<DD><I>
S. Kodase, S. Wang, and K. Shin
</I><P>
The model-based methodology has proven to be effective
for fast and low-cost development of embedded software.
In the model-based development process, transforming
a software structural model that describes the underlying
application, to an implementable runtime model is a
critical issue. Since the designed software will finally run
on the target platform, non-functional issues like schedulability,
timing constraints and resource requirements have
to be considered during the transformation. In this paper,
we propose a generic runtime model architecture that can
best satisfy the non-functional requirements of the system,
and a generic transformation method to convert a structural
model to a runtime model in such an architecture. The
transformation approach is based on the notion of end-to-end
computations performed by the system in response to
external stimuli. We demonstrate the advantages and effectiveness
of the proposed method by constructing a software
runtime model for a combined electronic throttle and airfuel
ratio control system.<P>
<DT>
<A HREF="../../df_files/04d_4.pdf" NAME="04d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
<DD><I>
O. Ogawa, K. Shinohara, Y. Watanabe, H. Niizuma,
T. Sasaki, Y. Takai, S. de Noyer, and P. Chauvet
</I><P>
For multimedia applications, the System LSI design
trend is to integrate an increasing number of applications
running on a single chip. Traditional architectures have
reached their limit in terms of performance. New
architectures must be explored to fulfill the system
application needs. Complex bus structures have been
introduced. These bus architectures open a much larger
exploration space than traditional hardware-software
partitioning trade-offs. We have been researching methods
to leverage these new architectural elements. We also
introduce a design environment to apply practical and
efficient methods in today's design flow. Two key
technologies are supporting our method and environment:
Automatic bus architecture synthesis for easy
configuration of bus architecture and transaction level of
abstraction for communication for improvement of
simulation performance. In this paper, we show the design
method, an overview of the design environment and its
usefulness through experimental results.<P>
<DT>
<A HREF="../../df_files/04d_5.pdf" NAME="04d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182]
<DD><I>
G. Palermo, C. Silvano, and V. Zaccaria
</I><P>
This paper describes the architectural exploration of the system-level
parameters for a MicroSPARC2-based embedded system. The overall
goal of the exploration task is to quickly identify the best
architecture of the embedded system in terms of both energy and
delay parameters, avoiding the comprehensive analysis of the
architectural design space. The Energy-Delay Product (EDP)
has been adopted as the evaluation metric to compare the alternative
architectures in terms of different cache memory and bus subsystems.
The exploration phase adopts an iterative local-search algorithm
based on the sensitivity analysis of the cost function with
respect to the tuning parameters of system architecture. The
exploration targets the architecture optimisation of the parameters
related to the cache memory and the bus sub-systems of an embedded
architecture based on the MicroSPARC2 architecture executing the
set of Mediabench benchmarks for multimedia applications. The
experimental results have shown a reduction up to nine orders of
magnitude of the number of design alternatives analyzed during
the exploration phase.<BR>
<B>Keywords:</B> Design Space Exploration, Embedded Systems,
Low-Power<P>
<DT>
<A HREF="../../df_files/04d_6.pdf" NAME="04d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]
<DD><I>
N. Drago, F. Fummi, M. Poncino, M. Monguzzi, and G. Perbellini
</I><P>
This paper describes a design methodology for the estimation
of bus performance of a tuplespace for factory automation.
The need of a tuplespace is motivated by the characteristics
of typical embedded architectures for factory automation.
We describe the features of a bus for embedded applications
and the problem of estimating its performance, and
present a rapid prototyping design methodology developed
for a qualitative and quantitative estimation. The methodology
is based on a mix of different modeling languages
such as Java, C++, SystemC and Network Simulator2
(NS2). Its application allows to estimate the expected performance
of the bus under design in relation to the developed
tuplespace.<P>
</DL>
<HR>
<H2>5D:<A NAME="sess5d">
Design Methodologies
</A></H2>
<I>
Moderators: V. Gerousis, Infineon, DE; E. Stoy, Ericsson, SE
</I><P>
<DL>
<DT>
<A HREF="../../df_files/05d_1.pdf" NAME="05d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Defining Cost Functions for Robust IC Design and Optimization [p. 196]
<DD><I>
ē. Brmen, J. Puhan, and T. Tuma
</I><P>
The ever increasing pace of analog IC design demands
efficient means of automated design and optimization. Especially
important is robust design. Its goal is to produce
circuits whose behaviour stays within some predefined
range when the manufacturing process variations and environmental
effects remain bounded. Most of the design process
is still handled by IC designers manually. We present a
simple mathematical formulation of the robust design and
optimization problem and its transformation into a constrained
optimization problem by means of penalty functions.
We illustrate the method on a robust differential amplifier
design problem. The resulting circuits show that a
computer not only can improve circuits designed by humans,
but is also capable of designing a circuit with very little
initial knowledge. Optimization runs resulted in circuits
with similar or even better performance when compared to
humanly designed circuits. The method can take advantage
of parallel processing, but is still efficient enough to be run
on a single computer.<P>
<DT>
<A HREF="../../df_files/05d_2.pdf" NAME="05d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SoC Design and Test Considerations [p. 202]
<DD><I>
M. Schrader and R. McConnell
</I><P>
Modern SoC Design for high-volume products
requires a strong focus on Design-for-Test and Design-for-Manufacturability.
We present a case study of an SoC
test concept, including a description of the DfT and DfM
features included in the SoC device and a brief motivation
for their utility.<P>
<DT>
<A HREF="../../df_files/05d_3.pdf" NAME="05d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A System to Validate and Certify Soft and Hard IP [p. 208]
<DD><I>
B. Laurent and T. Karger
</I><P>
With the increasing use of Intellectual Property (IP)
in the semiconductor industry, the demand to verify
IP for quality is high. This paper describes ipscreen,
a software tool that aims to both validate and certify
IP. Although extendable to all kinds of flows, checks
and commercial tools, ipscreen has been primarily designed
to comply with the standards that designs produced
within STMicroelectronics must adhere to. Both
soft and hard IP are targeted.<P>
<DT>
<A HREF="../../df_files/05d_4.pdf" NAME="05d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet
Type in a Noisy Channel [p. 214]
<DD><I>
M. Caldari, M. Conti, P. Crippa, G. Marozzi,
F. Di Gennaro, S. Orcioni, and C. Turchetti
</I><P>
High level design methodologies are needed to overcome the
complexity of System on Chip design. In this paper the SystemC
environment has been used to design a Bluetooth transceiver.
The high simulation speed allowed a high level performance
analysis of the IP developed and the definition of an algorithm
for selecting the best packet type in presence of channel noise.<P>
<DT>
<A HREF="../../df_files/05d_5.pdf" NAME="05d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Set Top Box SoC Design Methodology at STMicroelectronics [p. 220]
<DD><I>
F. Remond and P. Bricaud
</I><P>
In this paper we will review how the IP Reuse SoC design
methodology has evolved from its first introduction,
heavily based on IP Reuse to a state-of- the-art design
flow based on soft and hard IP block and floorplanning
tools. This will be illustrated in one complex SoC present
in the broadband communication market today, which is
a Set Top Box IC containing a proprietary 64-bits
processor and some general-purpose blocks, along with
dedicated functions specifically designed by
STMicroelectronics. In order to manage designs of this
complexity, a top-down, block-based design style, relying
on automatic floorplanning tools will be described. This
design style is using the classical 'divide-and-conquer'
strategy and is thus enabling a concurrent development
process, guaranteeing timing convergence and correct
chip assembly.<P>
<DT>
<A HREF="../../df_files/05d_6.pdf" NAME="05d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Verification of a Complex SoC: The PRO<SUP>3</SUP> Case-Study [p. 224]
<DD><I>
F. Andritsopoulos, G. Doumenis, C. Charopoulos, F. Karoubalis,
Y. Mitsos, F. Petreas, I. Theologitou, S. Perissakis, and D. Reisis
</I><P>
In this paper we present the experience gained from the
design and verification of a complex network processor. The
PRO3 processor 1 can operate in either ATM or IP based multiprotocol
networking environments, supporting link rates up
to 2.4 Gbps. We describe the methodology followed during
the verification process, from specifications to silicon prototype
test and highlight the problems encountered during the
post-layout procedure. To accommodate the application verification
a proprietary Debug Tool is integrated in the system.
The paper emphasizes the importance of the verification, addressing
it as a parallel process to system design, and highlights
the need for easy to verify designs.<P>
</DL>
<HR>
<H2>6D:<A NAME="sess6d">
System Level Design Case Studies
</A></H2>
<I>
Moderators: A. Reutter, Robert Bosch GmbH, DE; M. Poncino, Verona U, IT
</I><P>
<DL>
<DT>
<A HREF="../../df_files/06d_1.pdf" NAME="06d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Level Design of Embedded Controllers: Knock Detection,
A Case Study in the Automotive Domain [p. 232]
<DD><I>
L. Mangeruca, A. Ferrari, A. Sangiovanni-Vincentelli, M. Pennese, and A. Pierantoni
</I><P>
We present a case study in the design of automotive engine
controllers: the development of a knock detection algorithm
and its implementation in an optimized platform. The design
problem is complicated by the need of using heterogeneous
models of computation and different design environments. The
use of different design environments, one for functional design
and one for architectural design space exploration, requires to
transform a model of computation into another. We describe
how we solved this problem and we present the final design
with the trade-offs explored.<P>
<DT>
<A HREF="../../df_files/06d_2.pdf" NAME="06d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238]
<DD><I>
M. Verderber, A. Zemva, and D. Lampret
</I><P>
In this paper, we propose an optimized real-time MPEG-2
video decoder. The decoder has been implemented in one
FPGA device as a HW/SW partitioned system. We made
time/power-consumption analysis and optimization of the
MPEG-2 decoder. On the basis of the achieved results, we
decided for HW implementation of the IDCT and VLD
algorithms. Remaining parts were realized in SW with 32-bit
RISC processor. MPEG-2 decoder (RISC processor,
IDCT core, VLD core) has been described in
Verilog/VHDL and implemented in Virtex 1600E FPGA.
Finally, the decoder has been tested on the Flextronics
prototyping board.<P>
<DT>
<A HREF="../../df_files/06d_3.pdf" NAME="06d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
<DD><I>
S. Di Matteo, S. Rossi, R. Bonitz, E. Schler, P. Rao, and J. Helmschmidt
</I><P>
In this paper, we show the necessity of reconfigurable
hardware for data and signal processing in wireless
mobile terminals. We first identify the key processing
power requirements for realizing a third generation
wireless mobile terminal with multi-link and multistandard
capabilities. This is done on the basis of two
real-world applications: a flexible mobile rake
receiver for UMTS/W-CDMA and an OFDM decoder
for high-speed wireless LAN protocols. We present a
software-defined concept and a system implementation
for the signal processing in these applications. The
system is based on a DSP for control-flow oriented
tasks, dedicated hardware for predefined data-flow
oriented tasks and reconfigurable hardware for
software-defined data-flow oriented tasks. A new
coarse-grained approach is used to implement the
reconfigurable hardware, which is in the form of an
array of processing elements and also contains
resource management mechanisms. The features and
programming concepts of the reconfigurable
hardware are emphasized further in the text.<P>
<DT>
<A HREF="../../df_files/06d_4.pdf" NAME="06d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
<DD><I>
A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, and E. Martin
</I><P>
The design of high performance multimedia systems in a short
time force us to use IP's blocks in many designs. However, their
correct integration in a design implies more complex
verification problems. In this paper, we present a C++/SystemC
based simulation flow at multiple levels of abstraction. Our
approach is to use SystemC to describe both application and a
set of algorithmic IP cores to be incorporated throughout the
design flow. Our methodology supports design refinement
through four main abstraction levels, offers verification
techniques at each level and allows the use of EDA co-verification
tools. The use of C++/SystemC to model all parts of
the system provides great flexibility and enables faster
simulation compared to existing methodologies. An illustrative
case study for wavelet based compression system design shows
that our methodology supports efficient algorithmic
specification, where IP models can be easily incorporated,
modified and simulated in order to quickly evaluate alternative
system implementation.<P>
<DT>
<A HREF="../../df_files/06d_5.pdf" NAME="06d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]
<DD><I>
C. Sauer, M. Gries, C. Kulkarni, and K. Keutzer
</I><P>
Programming network processors remains an art due to
the variety of different network processor architectures
and due to little support to reason and explore implementations
on such architectures. We present a case study of
mapping an IPv4 forwarding switch application on the
Intel IXP1200 network processor and we compare this implementation
with an analytical model of both the application
and architecture used to evaluate different design
alternatives. Our results not only show that we are able to
model the IXP1200 and our application within 15% of the
accuracy compared to that of IXP1200 simulation, but also
find closely matching trends for different workloads. This
shows the clear potential of such analytical techniques for
design space exploration.<P>
<DT>
<A HREF="../../df_files/06d_6.pdf" NAME="06d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Solution for Hardware Emulation of Non Volatile Memory Macrocells [p. 262]
<DD><I>
A. Pirola
</I><P>
More and more the system verification makes use of
hardware emulation techniques that allow a speed up in
simulation performance up to thousand times. Typically, a
design is composed by several parts, most of them are
available as RTL code, other, mainly memories, only like
behavioral models. In this scenario co-emulation is necessary
to verify the heterogeneous system descriptions, but
this way most of the advantage of hardware emulation is
lost. This paper presents a solution for modeling the analog
array of a non volatile memory based on a VHDL synthesizable
description. The presented approach relies on
static RAMs and ROMs which models for emulation are
assumed to be available. The adoption of a synthesizable
model for the analog block makes possible the mapping of
the entire design on the emulator thus exploiting its performance
at full speed for efficient simulation sessions.<P>
</DL>
<HR>
<H2>7D:<A NAME="sess7d">
Analogue and Mixed Signal Methodology Design
</A></H2>
<I>
Moderators: L. Torres, LIRMM, FR; J.M. Portal, Marseille Polytech U, FR
</I><P>
<DL>
<DT>
<A HREF="../../df_files/07d_1.pdf" NAME="07d_1"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Bluetooth Transceiver Design with VHDL-AMS [p. 268]
<DD><I>
R. Ahola, D. Wallner, and M. Sida
</I><P>
This paper describes the design challenges of
BlueTraC<SUP>TM</SUP>, a low-cost, low-power radio transceiver and
the usage of mixed-signal/mixed-mode techniques and
behavioral modeling with ADVance MS (ADMS) from
Mentor Graphics to address and solve them. BlueTraC<SUP>TM</SUP>
from Spirea is a Bluetooth 1.1 compliant Class 2 radio
transceiver. In addition to all the required RF and analog
functions, the chip also includes a complete digital GFSK
modem, making it a very complex mixed-signal (MS)
system-on-chip (SoC). VHDL-AMS, the mixed-signal
IEEE 1076.1 standard modeling language, was used to
describe the SoC building blocks at different levels of
detail and complexity. This permitted us to perform top
level functional verification and debugging, as well as
detailed subsystem simulations throughout the design
process. We are presenting the concept and the results we
obtained, in terms of performance and accuracy. The
methodology that we deployed increased the confidence
in silicon success and allowed on time delivery.<P>
<DT>
<A HREF="../../df_files/07d_2.pdf" NAME="07d_2"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for
Non Volatile Memories Technologies [p. 274]
<DD><I>
P. Daglio and C. Roma
</I><P>
The wide range and rapid increase in the complexity of
EDA tools demand proven and safe design flows. This
paper presents a complete and fully qualified mixed-signal
top-down design flow for non volatile memory
applications. It has been successfully applied to an
Embedded Flash Macrocell based design as well as to a
14-bit analog/digital converter with digital non linearity
compensation manufactured in 0.18um proprietary
flash technology. One remarkable feature of the proposed
methodology is the high level of integration
among EDA tools from different vendors and internally
developed solutions. Mixed-signal domain has been
really explored at any level: functional, behavioural,
vhdl/schematic and post layout with parasitic components.
Furthermore, we propose a bottom-up methodology
to generate and validate VHDL-AMS models for
IP analog cells. All the illustrated features are integrated
in a design flow which provides full compatibility
and flexibility between analog and digital design
steps to cut down time-to-design, improve time-to-market
and streamline design quality.<P>
<DT>
<A HREF="../../df_files/07d_3.pdf" NAME="07d_3"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280]
<DD><I>
A. Mounir, A. Mostafa, and M. Fikry
</I><P>
Behavioural models selected from a predefined library
are automatically calibrated against transistor-level blocks
from a gigahertz-range PLL undergoing verification. The
calibrated behavioural models simulate at 10 to 200 times
the speed of the target blocks with insignificant loss of
accuracy. The technique shrinks the overall simulation
time of the assembled PLL by a factor of 120. We rely on a
set of carefully qualified, detailed behavioural models,
written in VHDL-AMS, each with a custom calibration
plan.<P>
<DT>
<A HREF="../../df_files/07d_4.pdf" NAME="07d_4"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]
<DD><I>
U. Knchel, T. Markwirth, R. Kakerow, R. Atukula, and J. Hartung
</I><P>
Today's mobile communication systems use sophisticated
signal processing to achieve high transmission rates.
Therefore a high complexity in the digital system part as
well as very accurate signal processing in the analog RF
subsystem is needed. So far analog and digital part are
developed separately. The increased performance requirements
demand now a common verification of the complete
system including analog and digital parts. At the design of
an IEEE 802.11a wireless LAN receiver it is demonstrated,
how the RF receiver part is tested in the system level simulation.
Different simulation tools are used. The simulation
results show the impact of properties of the RF part on the
system performance. Experiences from the tool evaluation
are presented.<P>
<DT>
<A HREF="../../df_files/07d_5.pdf" NAME="07d_5"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
<DD><I>
M. McCorquodale, F. Gebara, K. Kraver, E. Marsman, R. Senger, and R. Brown
</I><P>
An overview of microsystems technology is presented
along with a discussion of the recent trends and challenges
associated with its development. A typical bottom-up
design methodology is described and we propose, in contrast,
an efficient and effective top-down methodology. We
illustrate its implementation with the development of a
microsystem design that has been completed and fabricated
in CMOS technology. Gaps in the tool capabilities
are identified and suggestions for future directions in CAD
tool support for microsystems technology are presented.<P>
<DT>
<A HREF="../../df_files/07d_6.pdf" NAME="07d_6"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
<DD><I>
R. Iskander, M. Aly, M. Magdy, N. Hassan, N. Soliman, S. Moussa, and M. Dessouky
</I><P>
In this paper, a simulation-based synthesis tool,
AMIGO, for analog cell sizing is presented. AMIGO is
based upon genetic optimization techniques adapted to
circuit sizing. A framework has been developed using
TCL/TK language that allows the designer to set the
optimization problem, define complex constraint
functions, watch the progress of optimization, and finally
view results. To increase design reliability a sizing-rule
pre-processor is incorporated in the tool to automatically
generate topology related constraints specific to analog
building blocks. Different approaches of using circuit
optimizers are demonstrated through the synthesis of
three different analog cells: a latched-type comparator, a
folded cascode opamp and a switched-capacitor
integrator. AMIGO showed to be a successful synthesis
tool that can be part of a more general
synthesis/migration flow. <P>
</DL>
]]>