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DATE 2003 :
[ <A HREF="dateabs.htm">Abstracts</A> ]
[ <A HREF="datesess.htm">Session Index</A> ]
[ <A HREF="dateai.htm">Author Index</A> ]</H3>
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<H2>DATE 2003 TABLE OF CONTENTS</H2>
<B>
Sessions:
[<A HREF="#plenary">Plenary</A>]
[<A HREF="#sess1a">1A</A>]
[<A HREF="#sess1b">1B</A>]
[<A HREF="#sess1c">1C</A>]
[<A HREF="#sess1f">1F</A>]
[<A HREF="#sess2a">2A</A>]
[<A HREF="#sess2b">2B</A>]
[<A HREF="#sess2c">2C</A>]
[<A HREF="#sess2e">2E</A>]
[<A HREF="#sess2f">2F</A>]
[<A HREF="#sess3a">3A</A>]
[<A HREF="#sess3b">3B</A>]
[<A HREF="#sess3c">3C</A>]
[<A HREF="#sess3f">3F</A>]
[<A HREF="#sess4a">4A</A>]
[<A HREF="#sess4b">4B</A>]
[<A HREF="#sess4c">4C</A>]
[<A HREF="#sess4e">4E</A>]
[<A HREF="#sess4f">4F</A>]
[<A HREF="#sess5a">5A</A>]
[<A HREF="#sess5b">5B</A>]
[<A HREF="#sess5c">5C</A>]
[<A HREF="#sess5e">5E</A>]
[<A HREF="#sess5f">5F</A>]
[<A HREF="#sess6a">6A</A>]
[<A HREF="#sess6b">6B</A>]
[<A HREF="#sess6c">6C</A>]
[<A HREF="#sess6e">6E</A>]
[<A HREF="#sess6f">6F</A>]
[<A HREF="#sess7a">7A</A>]
[<A HREF="#sess7b">7B</A>]
[<A HREF="#sess7c">7C</A>]
[<A HREF="#sess7e">7E</A>]
[<A HREF="#sess7f">7F</A>]
[<A HREF="#sess8a">8A</A>]
[<A HREF="#sess8b">8B</A>]
[<A HREF="#sess8c">8C</A>]
[<A HREF="#sess8d">8D</A>]
[<A HREF="#sess8e">8E</A>]
[<A HREF="#sess8f">8F</A>]
[<A HREF="#sess9a">9A</A>]
[<A HREF="#sess9b">9B</A>]
[<A HREF="#sess9c">9C</A>]
[<A HREF="#sess9d">9D</A>]
[<A HREF="#sess9e">9E</A>]
[<A HREF="#sess9f1">9F1</A>]
[<A HREF="#sess9f2">9F2</A>]
[<A HREF="#sess10a">10A</A>]
[<A HREF="#sess10b">10B</A>]
[<A HREF="#sess10c">10C</A>]
[<A HREF="#sess10d">10D</A>]
[<A HREF="#sess10e">10E</A>]
[<A HREF="#sess10f">10F</A>]
[<A HREF="#poster">Poster</A>]<P>
<A HREF="../../pdffiles/execom.pdf">DATE Executive Committee</A><BR>
<A HREF="../../pdffiles/techchair.pdf">Technical Program Chairs</A><BR>
<A HREF="../../pdffiles/venspon.pdf">Vendors Committee</A><BR>
<A HREF="../../pdffiles/venspon.pdf">DATE Sponsor Committee</A><BR>
<A HREF="../../pdffiles/techcom.pdf">Technical Program Committee</A><BR>
<A HREF="../../pdffiles/reviewer.pdf">Reviewers</A><BR>
<A HREF="../../pdffiles/welcome.pdf">Welcome to DATE 2003</A><BR>
<A HREF="../../pdffiles/bestppr.pdf">Best Paper Awards</A><BR>
<A HREF="../../pdffiles/tutorial.pdf">Tutorials</A><BR>
<A HREF="../../pdffiles/courses.pdf">Master Courses</A><BR>
<A HREF="../../pdffiles/cfp.pdf">Call for Papers DATE 2004</A><P>
</B>
</DL>
<HR>
<H2>Plenary: <A HREF="dateabs.htm#plenary" NAME="plenary">
Keynote Session
</A></H2>
<I>
Moderator: D. Verkest, IMEC, BE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#keynote1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/keynote1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
IC Design Challenges for Ambient Intelligence [p. 2]
<DD><I>
E. Aarts and R. Roovers
</I><P>
<DT>
<A HREF="dateabs.htm#keynote2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/keynote2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Semiconductor Challenges [p. 8]
<DD><I>
A. Cuomo
</I><P>
</DL>
<HR>
<H2>1A:<A HREF="dateabs.htm#sess1a" NAME="sess1a">
Hot Topic: Ambient Intelligence Visions and Achievements:
Linking Abstract Ideas to Real-World Concepts
</A></H2>
<I>
Organizer/Moderator: M. Lindwer, Philips, NL<BR>
Speakers:<BR>
R. Zimmermann, European Union, Unit for Microelectronics, BE<BR>
D. Marculescu, CMU, US<BR>
R. Marculescu, CMU, US<BR>
S. Jung, Infineon, DE<BR>
E. Cantatore, Philips, NL<BR>
T. Basten, Eindhoven U, NL
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#01a"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
<DD><I>
Panel Statement [p. 10]
</I><P>
</DL>
<HR>
<H2>1B: <A HREF="dateabs.htm#sess1b" NAME="sess1b">
Energy-Efficient Memory Systems
</A></H2>
<I>
Moderators: V. Narayanan, Penn State U, US; P. Fugger, Infineon, DE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Improving the Efficiency of Memory Partitioning by Address Clustering [p. 18]
<DD><I>
A. Macii, E. Macii, and M. Poncino
</I><P>
<DT>
<A HREF="dateabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]
<DD><I>
A. Macii, E. Macii, F. Crudo, and R. Zafalon
</I><P>
<DT>
<A HREF="dateabs.htm#01b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power Efficiency through Application-Specific Instruction Memory Transformations [p. 30]
<DD><I>
P. Petrov and A. Orailoglu
</I><P>
<DT>
<A HREF="dateabs.htm#01b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Energy Data Management for Different On-Chip Memory Levels in
Multi-Context Reconfigurable Architectures [p. 36]
<DD><I>
M. Snchez-lez, M. Fernndez, M. Anido, H. Du, R. Hermida, and N. Bagherzadeh
</I><P>
</DL>
<HR>
<H2>1C: <A HREF="dateabs.htm#sess1c" NAME="sess1c">
Embedded Tutorial: Circuit, Platform Design and Test Challenges in
Technologies Beyond 90nm
</A></H2>
<I>
Organizer/Moderator: S. Kundu, Intel, US<BR>
Speakers:<BR>
B. Grundmann, Intel Corporation, US<BR>
R. Galivanche, Principal Engineer, Intel Corporation, US
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#01c"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01c.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Panel Statement [p. 44]
</DL>
<HR>
<H2>1F:<A HREF="dateabs.htm#sess1f" NAME="sess1f">
Uncertainty
</A></H2>
<I>
Moderators: F. Johannes, TU Munich, DE; C. Sechen, Washington U, US
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#01f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Global Wire Bus Configuration with Minimum Delay Uncertainty [p. 50]
<DD><I>
L. Huang, H. Chen, and D. Wong
</I><P>
<DT>
<A HREF="dateabs.htm#01f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Timing Verification with Crosstalk for Transparently Latched Circuits [p. 56]
<DD><I>
H. Zhou
</I><P>
<DT>
<A HREF="dateabs.htm#01f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Statistical Timing Analysis Using Bounds [p. 62]
<DD><I>
A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula
</I><P>
<DT>
<A HREF="dateabs.htm#01f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reduced Delay Uncertainty in High Performance Clock Distribution Networks [p. 68]
<DD><I>
D. Velenis, E. Friedman, and M. Papaefthymiou
</I><P>
</DL>
<HR>
<H2>2A: <A HREF="dateabs.htm#sess2a" NAME="sess2a">
Hot Topic: Scaling into Ambient Intelligence
</A></H2>
<I>
Organizer/Moderator: T. Basten, TU Eindhoven, NL<BR>
Speakers:<BR>
A. Chandrakasan, MIT, US<BR>
M. Lindwer, Philips, NL<BR>
J. Liu, PARC, US<BR>
L. Benini, DEIS ö Bologna U, IT<BR>
R. Min, MIT, US<BR>
F. Zhao, Palo Alto Research Center (PARC), US
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#02a"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Panel Statement [p. 76]
</DL>
<HR>
<H2>2B: <A HREF="dateabs.htm#sess2b" NAME="sess2b">
Power-Aware Design and Synthesis
</A></H2>
<I>
Moderators: R. Zafalon, STMicroelectronics, IT; D. Marculescu, CMU, US
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Masking the Energy Behavior of DES Encryption [p. 84]
<DD><I>
H. Saputra, S. Vijaykrishnan, M. Kandemir, M. Irwin, R. Brooks, S. Kim, and W. Zhang
</I><P>
<DT>
<A HREF="dateabs.htm#02b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems [p. 90]
<DD><I>
D. Wu, B. Al-Hashimi, and P. Eles
</I><P>
<DT>
<A HREF="dateabs.htm#02b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications [p. 96]
<DD><I>
L. Chiou, S. Bhunia, and K. Roy
</I><P>
</DL>
<HR>
<H2>2C: <A HREF="dateabs.htm#sess2c" NAME="sess2c">
Test Data Compression
</A></H2>
<I>
Moderators: M. Flottes, LIRMM, FR; P. Prinetto, Politecnico di Torino, IT
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Virtual Compression through Test Vector Stitching for Scan Based Design [p. 104]
<DD><I>
W. Rao and A. Orailoglu
</I><P>
<DT>
<A HREF="dateabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]
<DD><I>
N. Oh, R. Kapur, T. Williams, and J. Sproch
</I><P>
<DT>
<A HREF="dateabs.htm#02c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Technique for High Ratio LZW Compression [p. 116]
<DD><I>
M. Knieser, D. Weyer, R. McIntyre, F. Wolff, and C. Papachristou
</I><P>
<DT>
<A HREF="dateabs.htm#02c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Fast Computation of Data Correlation Using BDDs [p. 122]
<DD><I>
Z. Zeng, Q. Zhang, I. Harris, and M. Ciesielski
</I><P>
</DL>
<HR>
<H2>2E: <A HREF="dateabs.htm#sess2e" NAME="sess2e">
Operating System Abstraction and Targeting (Embedded Software Forum)
</A></H2>
<I>
Moderators: S. Yoo, TIMA Laboratory, FR; M. Coppola, STMicroelectronics, IT
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#02e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
RTOS Modeling for System Level Design [p. 130]
<DD><I>
A. Gerstlauer, H. Yu, and D. Gajski
</I><P>
<DT>
<A HREF="dateabs.htm#02e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling and Integration of Peripheral Devices in Embedded Systems [p. 136]
<DD><I>
S. Wang, S. Malik, and R. Bergamaschi
</I><P>
<DT>
<A HREF="dateabs.htm#02e_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Systematic Embedded Software Generation from SystemC [p. 142]
<DD><I>
F. Herrera, H. Posadas, P. Snchez, and E. Villar
</I><P>
</DL>
<HR>
<H2>2F: <A HREF="dateabs.htm#sess2f" NAME="sess2f">
Analysis of Jitter and Noise for Analogue Systems and
SD Modelling and Simulation
</A></H2>
<I>
Moderators: G. Vandersteen, IMEC, BE; H. Graeb, TU Munich, DE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#02f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]
<DD><I>
Y. Xu, X. Li, P. Li, and L. Pileggi
</I><P>
<DT>
<A HREF="dateabs.htm#02f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]
<DD><I>
M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, K. Gullapalli, and B. Mulvaney
</I><P>
<DT>
<A HREF="dateabs.htm#02f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Model of Computation for Continuous-Time Delta-Sigma Modulators [p. 162]
<DD><I>
E. Martens and G. Gielen
</I><P>
<DT>
<A HREF="dateabs.htm#02f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]
<DD><I>
R. Castro-Lpez, F. Fernndez, F. Medeiro, and A. Rodrguez-Vzquez
</I><P>
</DL>
<HR>
<H2>3A: <A HREF="dateabs.htm#sess3a" NAME="sess3a">
Hot Topic: Securing Mobile Appliance:
New Challenges for the System Designer
</A></H2>
<I>
Organizer/Moderator: A. Raghunathan, NEC, US<BR>
Speakers:<BR>
S. Ravi, NEC, US<BR>
S. Hattangady, Texas Instruments, US<BR>
J.-J. Quisquater, UC de Louvain, BE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#03a"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Panel Statement [p. 176]
</DL>
<HR>
<H2>3B: <A HREF="dateabs.htm#sess3b" NAME="sess3b">
Scheduling and Analysis of Embedded Systems
</A></H2>
<I>
Moderators: V. Mooney, Georgia IT, US; A. Jantsch, Royal IT, SE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#03b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster
Distributed Embedded Systems [p. 184]
<DD><I>
P. Pop, P. Eles, and Z. Peng
</I><P>
<DT>
<A HREF="dateabs.htm#03b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs [p. 190]
<DD><I>
S. Chakraborty, S. Kuenzli, and L. Thiele
</I><P>
<DT>
<A HREF="dateabs.htm#03b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration [p. 196]
<DD><I>
G. Logothetis and K. Schneider
</I><P>
<DT>
<A HREF="dateabs.htm#03b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures [p. 204]
<DD><I>
B. Rinner, M. Schmid, and R. Weiss
</I><P>
</DL>
<HR>
<H2>3C: <A HREF="dateabs.htm#sess3c" NAME="sess3c">
Recent Advances in DFT and BIST
</A></H2>
<I>
Moderators: A. Benso, Politecnico di Torino, IT; I.G. Harris, Massachusetts U, Amherst, US
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#03c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers [p. 212]
<DD><I>
M. Nummer and M. Sachdev
</I><P>
<DT>
<A HREF="dateabs.htm#03c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending JTAG for Testing Signal Integrity in SoCs [p. 218]
<DD><I>
N. Ahmed, M. Tehranipour, and M. Nourani
</I><P>
<DT>
<A HREF="dateabs.htm#03c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
EBIST: A Novel Test Generator with Built-In Fault Detection Capability [p. 224]
<DD><I>
D. Pradhan, C. Liu, and K. Chakraborty
</I><P>
<DT>
<A HREF="dateabs.htm#03c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with
Applications to System-On-Chip Fault Diagnosis [p. 230]
<DD><I>
C. Liu and K. Chakrabarty
</I><P>
</DL>
<HR>
<H2>3F: <A HREF="dateabs.htm#sess3f" NAME="sess3f">
Analogue and RF Modelling, Simulation and Optimisation
</A></H2>
<I>
Moderators: F.V. Fernandez, IMSE CNM, ES; R. Schwencker, Infineon, DE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#03f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with
Sampling Phase-Frequency Detectors [p. 238]
<DD><I>
P. Vanassche, G. Gielen, and W. Sansen
</I><P>
<DT>
<A HREF="dateabs.htm#03f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]
<DD><I>
M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, and J. Mulvaney
</I><P>
<DT>
<A HREF="dateabs.htm#03f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generalized Posynomial Performance Modeling [p. 250]
<DD><I>
T. Eeckelaert, W. Daems, G. Gielen, and W. Sansen
</I><P>
<DT>
<A HREF="dateabs.htm#03f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Holmes: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits [p. 256]
<DD><I>
B. De Smedt and G. Gielen
</I><P>
</DL>
<HR>
<H2>4A: <A HREF="dateabs.htm#sess4a" NAME="sess4a">
Architectural Level Synthesis
</A></H2>
<I>
Moderators: P.Y.K. Cheung, Imperial College London, UK; J. Teich, Erlangen-Nuremberg U, DE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Allocation to Minimize Internal Hardware Wastage [p. 264]
<DD><I>
M. Molina, J. Mendas, and R. Hermida
</I><P>
<DT>
<A HREF="dateabs.htm#04a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]
<DD><I>
S. Gupta, N. Dutt, R. Gupta, and A. Nicolau
</I><P>
<DT>
<A HREF="dateabs.htm#04a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Distributed Synchronous Control Units for Dataflow Graphs under Allocation of
Telescopic Arithmetic Units [p. 276]
<DD><I>
E. Kim, H. Saito, H. Nakamura, T. Nanya, J. Lee, and D. Lee
</I><P>
<DT>
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Automated Bus Generation for Multiprocessor SoC Design [p. 282]
<DD><I>
K. Ryu and V. Mooney III
</I><P>
</DL>
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<H2>4B: <A HREF="dateabs.htm#sess4b" NAME="sess4b">
Scheduling in Reconfigurable Computing
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<I>
Moderators: A. Koch, TU Braunschweig, DE; G. Koch, Bridges2Silicon, DE
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Online Scheduling for Block-Partitioned Reconfigurable Devices [p. 290]
<DD><I>
H. Walder and M. Platzner
</I><P>
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Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures
Using Modulo Scheduling [p. 296]
<DD><I>
B. Mei, H. De Man, R. Lauwereins, S. Vernalde, and D. Verkest
</I><P>
<DT>
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Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems [p. 302]
<DD><I>
S. Lange and U. Kebschull
</I><P>
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<H2>4C: <A HREF="dateabs.htm#sess4c" NAME="sess4c">
Delay Testing and Diagnosis
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<I>
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A Method of Test Generation for Path Delay Faults Using Stuck-At Fault Test Generation Algorithms [p. 310]
<DD><I>
S. Ohtake, K. Ohtani, and H. Fujiwara
</I><P>
<DT>
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A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification [p. 316]
<DD><I>
M. Syal and M. Hsiao
</I><P>
<DT>
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Non-Enumerative Path Delay Fault Diagnosis [p. 322]
<DD><I>
S. Padmanaban and S. Tragoudas
</I><P>
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Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step [p. 328]
<DD><I>
A. Krstic, L. Wang, K. Cheng, J. Liou, and M. Abadir
</I><P>
</DL>
<HR>
<H2>4E: <A HREF="dateabs.htm#sess4e" NAME="sess4e">
Embedded Tutorial: Embedded Operating Systems for SoC
(Embedded Software Forum)
</A></H2>
<I>
Organizer: A. Jerraya, TIMA Laboratory, FR<BR>
Moderator: J. Madsen, TU Denmark, DK
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Introduction to Hardware Abstraction Layers for SoC [p. 336]
<DD><I>
S. Yoo and A. Jerraya
</I><P>
<DT>
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<A HREF="../../pdffiles/04e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Hardware/Software Partitioning of Operating Systems [p. 338]
<DD><I>
V. Mooney III
</I><P>
<DT>
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Embedded Software in Digital AM-FM Chipset [p. 340]
<DD><I>
M. Sarlotte, B. Candaele, J. Quevremont, and D. Merel
</I><P>
</DL>
<HR>
<H2>4F: <A HREF="dateabs.htm#sess4f" NAME="sess4f">
Networks-on-Chip
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<I>
Moderators: P. Ienne, EPF Lausanne, CH; E. Verhulst, Eonic Solutions GmbH, DE
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Packetized On-Chip Interconnect Communication Analysis for MPSoC [p. 344]
<DD><I>
T. Ye, G. De Micheli, and L. Benini
</I><P>
<DT>
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Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for
Networks On Chip [p. 350]
<DD><I>
E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen,
J. van Meerbergen, P. Wielage, and E. Waterlander
</I><P>
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Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors [p. 356]
<DD><I>
F. Gilbert, M. Thul, and N. Wehn
</I><P>
</DL>
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<H2>5A: <A HREF="dateabs.htm#sess5a" NAME="sess5a">
System Level Modelling
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<I>
Moderators: C. Delgado Kloos, Carlos III de Madrid U, ES; E. Villar, Cantabria, U, ES
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Development and Application of Design Transformations in ForSyDe [p. 364]
<DD><I>
I. Sander, A. Jantsch, and Z. Lu
</I><P>
<DT>
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System Level Specification in Lava [p. 370]
<DD><I>
S. Singh
</I><P>
<DT>
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<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Formal Semantics of Synchronous SystemC [p. 376]
<DD><I>
A. Salem
</I><P>
<DT>
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<A HREF="../../pdffiles/05a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated [p. 382]
<DD><I>
F. Doucet, R. Gupta, and S. Shukla
</I><P>
<DT>
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<A HREF="../../pdffiles/05a_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SystemC-AMS Requirements, Design Objectives and Rationale [p. 388]
<DD><I>
A. Vachoux, C. Grimm, and K. Einwich
</I><P>
</DL>
<HR>
<H2>5B: <A HREF="dateabs.htm#sess5b" NAME="sess5b">
Hot Topic: Runtime Reconfigurable Systems on Chip - An Industry Perspective
</A></H2>
<I>
Organizer/Moderator: I. Bolsens, Xilinx, US
</I><P>
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<A HREF="../../pdffiles/05b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Parallel Processing Architectures for Reconfigurable Systems [p. 396]
<DD><I>
K. Vissers
</I><P>
<DT>
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<A HREF="../../pdffiles/05b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Different Approaches to Add Reconfigurability in a SoC Architecture [p. 398]
<DD><I>
B. Gupta and M. Borgatti
</I><P>
<DT>
<A HREF="dateabs.htm#05b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Lightweight Approach for Embedded Reconfiguration of FPGAs [p. 399]
<DD><I>
B. Blodget, S. McMillan, and P. Lysaght
</I><P>
</DL>
<HR>
<H2>5C: <A HREF="dateabs.htm#sess5c" NAME="sess5c">
Hot Topic: Creating Value Through Test
</A></H2>
<I>
Organizer/Moderator: E.J. Marinissen, Philips, NL<BR>
Speakers:<BR>
B. Vermeulen, Philips, NL<BR>
R. Madge, LSI Logic, US<BR>
M. Kessler and M. Mller, IBM Boeblingen, DE
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Panel Statement [p. 402]
</DL>
<HR>
<H2>5E: <A HREF="dateabs.htm#sess5e" NAME="sess5e">
Software Optimisation for Embedded Systems (Embedded Software Forum)
</A></H2>
<I>
Moderators: R. Leupers, RWTH Aachen, DE; J.C. Lopez, Castilla-La Mancha, ES
</I><P>
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<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Control Flow Driven Splitting of Loop Nests at the Source Code Level [p. 410]
<DD><I>
H. Falk and P. Marwedel
</I><P>
<DT>
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<A HREF="../../pdffiles/05e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Data Space Oriented Scheduling in Embedded Systems [p. 416]
<DD><I>
M. Kandemir, G. Chen, W. Zhang, and I. Kolcu
</I><P>
<DT>
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Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines:
Predication, Speculation and Modulo Scheduling [p. 422]
<DD><I>
S. Pillai and M. Jacome
</I><P>
<DT>
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<A HREF="../../pdffiles/05e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Hash Table Based Approach to Avoid State Space Explosion in
History Driven Quasi-Static Scheduling [p. 428]
<DD><I>
A. Lomea, M. Lpez-Vallejo, Y. Watanabe, and A. Kondratyev
</I><P>
</DL>
<HR>
<H2>5F: <A HREF="dateabs.htm#sess5f" NAME="sess5f">
Global Approaches to Layout Synthesis
</A></H2>
<I>
Moderators: I. Markov, Michigan U, US; J. Lienig, TU Dresden, DE
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Time Budgeting in a Wireplanning Context [p. 436]
<DD><I>
J. Westra, R. Otten, D. Jongeneel, and C. Visweswariah
</I><P>
<DT>
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<A HREF="../../pdffiles/05f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Interconnect Planning with Local Area Constrained Retiming [p. 442]
<DD><I>
R. Lu and C. Koh
</I><P>
<DT>
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A Novel Metric for Interconnect Architecture Performance [p. 448]
<DD><I>
P. Dasgupta, A. Kahng, and S. Muddu
</I><P>
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<H2>6A: <A HREF="dateabs.htm#sess6a" NAME="sess6a">
Platform Design and IP Reuse Methods
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Specification of Non-Functional Intellectual Property Components [p. 456]
<DD><I>
J. Zhu and W. Mong
</I><P>
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<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Profile-Driven Selective Code Compression [p. 462]
<DD><I>
Y. Xie, W. Wolf, and H. Lekatsas
</I><P>
<DT>
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<A HREF="../../pdffiles/06a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]
<DD><I>
C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi
</I><P>
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<H2>6B: <A HREF="dateabs.htm#sess6b" NAME="sess6b">
Panel: Reconfigurable Computing - Different Perspectives
</A></H2>
<I>
Organizer: W. Rosenstiel, Tuebingen U/FZI, DE<BR>
Moderator: R. Lauwereins, IMEC, BE<BR>
Panellists:<BR>
I. Bolsens, Xilinx, US<BR>
C. Rowen, Tensilica, US<BR>
Y. Tanurhan, Actel, US<BR>
K. Vissers, Chameleon Systems, US<BR>
S. Wang, Axis Systems, US
</I><P>
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Panel Statement [p. 476]
</DL>
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<H2>6C: <A HREF="dateabs.htm#sess6c" NAME="sess6c">
Analogue and Defect-Oriented Testing
</A></H2>
<I>
Moderators: R. Galivanche, Intel, US; A. Richardson, Lancaster U, UK
</I><P>
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RF-BIST: Loopback Spectral Signature Analysis [p. 478]
<DD><I>
D. Lupea, U. Pursche, and H. Jentschel
</I><P>
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Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]
<DD><I>
Z. Al-Ars, A. van de Goor, J. Braun, and D. Richter
</I><P>
<DT>
<A HREF="dateabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Modeling Cross-Talk Faults [p. 490]
<DD><I>
S. Zachariah, Y. Chang, S. Kundu, and C. Tirumurti
</I><P>
<DT>
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Techniques for Automatic on Chip Closed Loop Transfer Function Monitoring for
Embedded Charge Pump Phase Locked Loops [p. 496]
<DD><I>
M. Burbidge, A. Richardson, and J. Tijou
</I><P>
</DL>
<HR>
<H2>6E: <A HREF="dateabs.htm#sess6e" NAME="sess6e">
Energy Aware Software Techniques (Embedded Software Forum)
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<I>
Moderators: J. Henkel, NEC, US; P. Marwedel, Dortmund U, DE
</I><P>
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<A HREF="../../pdffiles/06e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and
General Purpose Software Applications [p. 504]
<DD><I>
V. Rapaka and D. Marculescu
</I><P>
<DT>
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Runtime Code Parallelization for On-Chip Multiprocessors [p. 510]
<DD><I>
M. Kandemir, W. Zhang, and M. Karakoy
</I><P>
<DT>
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SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on
Multi-Processor Platforms [p. 516]
<DD><I>
P. Marchal, F. Catthoor, D. Bruni, L. Benini, J. Gomez, L. Piuel, and H. Corporaal
</I><P>
</DL>
<HR>
<H2>6F: <A HREF="dateabs.htm#sess6f" NAME="sess6f">
Interconnect Modelling and Signal Integrity
</A></H2>
<I>
Moderators: L.M. Silveira, INESC ID/IST, PT; J.R. Phillips, Cadence, US
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<A HREF="../../pdffiles/06f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling and Evaluation of Substrate Noise Induced by Interconnects [p. 524]
<DD><I>
F. Martorell, D. Mateo, and X. Aragons
</I><P>
<DT>
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Model-Order Reduction Based on PRONY's Method [p. 530]
<DD><I>
M. Mansour and A. Mehrotra
</I><P>
<DT>
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<A HREF="../../pdffiles/06f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]
<DD><I>
S. Grivet-Talocia, I. Stievano, F. Canavero, and I. Maio
</I><P>
<DT>
<A HREF="dateabs.htm#06f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]
<DD><I>
T. Lv, W. Wolf, J. Henkel, and H. Lekatsas
</I><P>
</DL>
<HR>
<H2>7A: <A HREF="dateabs.htm#sess7a" NAME="sess7a">
System Level Simulation
</A></H2>
<I>
Moderators: B.M. Al-Hashimi, Southampton U, UK; M. Rencz, TU Budapest, HU
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<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and
Simulation Environment Abstraction Layer [p. 550]
<DD><I>
S. Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, and A. Jerraya
</I><P>
<DT>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation [p. 556]
<DD><I>
W. Qin and S. Malik
</I><P>
<DT>
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<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Instruction Set Emulation for Rapid Prototyping of SoCs [p. 562]
<DD><I>
J. Schnerr, G. Haug, and W. Rosenstiel
</I><P>
</DL>
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<H2>7B: <A HREF="dateabs.htm#sess7b" NAME="sess7b">
Design Space Exploration for Reconfigurable Computing
</A></H2>
<I>
Moderators: P. Lysaght, Xilinx, US; S. Vernalde, IMEC, BE
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<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Hardware/Software Design Space Exploration for a Reconfigurable Processor [p. 570]
<DD><I>
A. La Rosa, L. Lavagno, and C. Passerone
</I><P>
<DT>
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From C Programs to the Configure-Execute Model [p. 576]
<DD><I>
J. Cardoso and M. Weinhardt
</I><P>
<DT>
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<A HREF="../../pdffiles/07b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
FPGA-Based Implementation of a Serial RSA Processor [p. 582]
<DD><I>
A. Mazzeo, L. Romano, G. Saggese, and N. Mazzocca
</I><P>
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<H2>7C: <A HREF="dateabs.htm#sess7c" NAME="sess7c">
On-Line Testing and Self-Repair
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Moderators: L. Bouzaida, STMicroelectronics, FR; A. Paschalis, Athens U, GR
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Optimal Reconfiguration Functions for Column or Data-Bit Built-In Self-Repair [p. 590]
<DD><I>
M. Nicolaidis, N. Achouri, and S. Boutobza
</I><P>
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Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric [p. 596]
<DD><I>
P. Oikonomakos, M. Zwolinski, and B. Al-Hashimi
</I><P>
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An Accurate Analysis of the Effects of Soft Errors in the Instruction and
Data Caches of a Pipelined Microprocessor [p. 602]
<DD><I>
M. Rebaudengo, M. Sonza Reorda, and M. Violante
</I><P>
<DT>
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High Speed and Highly Testable Parallel Two -Rail Code Checker [p. 608]
<DD><I>
M. Omaa, D. Rossi, and C. Metra
</I><P>
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<H2>7E: <A HREF="dateabs.htm#sess7e" NAME="sess7e">
Hot Topic: Safe Automotive Software Development (Embedded Software Forum)
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Safe Automotive Software Development [p. 616]
<DD><I>
K. Tindell, H. Kopetz, F. Wolf, and R. Ernst
</I><P>
</DL>
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<H2>7F: <A HREF="dateabs.htm#sess7f" NAME="sess7f">
Mixed-Signal Design Techniques
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<I>
Moderators: A. Kaiser, IEMN-ISEN, FR; T. Ifstroem, Robert Bosch GmbH, DE
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Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]
<DD><I>
P. Dobrovolnŕ, G. Vandersteen, P. Wambacq, and S. Donnay
</I><P>
<DT>
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Linear Model-Based Error Identification and Calibration for Data Converters [p. 630]
<DD><I>
C. Wegener and M. Kennedy
</I><P>
<DT>
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Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters [p. 636]
<DD><I>
M. Albiol, J. Gonzlez, and E. Alarcn
</I><P>
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Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control
Loop in a 5 GHz WLAN Receiver [p. 642]
<DD><I>
W. Eberle, H. De Man, G. Vandersteen, P. Wambacq, G. Gielen, and S. Donnay
</I><P>
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<HR>
<H2>8A: <A HREF="dateabs.htm#sess8a" NAME="sess8a">
Design Space Exploration
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<I>
Moderators: H. Hsieh, UC Riverside, US; W. Kruijtzer, Philips, NL
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Analytical Design Space Exploration of Caches for Embedded Systems [p. 650]
<DD><I>
A. Ghosh and T. Givargis
</I><P>
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Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]
<DD><I>
V. Zivkovic, E. Deprettere, E. de Kock, and P. van der Wolf
</I><P>
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Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]
<DD><I>
L. Vanzago, J. Cambonie, B. Bhattacharya, and L. Lavagno
</I><P>
<DT>
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A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]
<DD><I>
W. Fornaciari, F. Salice, P. Micheli, and L. Zampella
</I><P>
<DT>
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Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]
<DD><I>
Y. Le Moullec, J. Diguet, J. Philippe, N. Ben Amor, and M. Abid
</I><P>
</DL>
<HR>
<H2>8B: <A HREF="dateabs.htm#sess8b" NAME="sess8b">
Low Power Architectures
</A></H2>
<I>
Moderators: W. Nebel, OFFIS/Oldenburg U, DE; J. Henkel, NEC, US
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Energy Estimation for Extensible Processors [p. 682]
<DD><I>
Y. Fei, N. Jha, S. Ravi, and A. Raghunathan
</I><P>
<DT>
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Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of
Regular NoC Architectures [p. 688]
<DD><I>
J. Hu and R. Marculescu
</I><P>
<DT>
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Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface [p. 694]
<DD><I>
W. Cheng and M. Pedram
</I><P>
<DT>
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MRPF: An Architectural Transformation for Synthesis of High-Performance and
Low-Power Digital Filters [p. 700]
<DD><I>
H. Choo, K. Roy, and K. Muhammad
</I><P>
<DT>
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Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]
<DD><I>
D. Bertozzi, L. Benini, A. Raghunathan, and S. Ravi
</I><P>
</DL>
<HR>
<H2>8C: <A HREF="dateabs.htm#sess8c" NAME="sess8c">
System-on-Chip Testing
</A></H2>
<I>
Moderators: P. Harrod, ARM, UK; S. Shoukourian, VirageLogic International, AR
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Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]
<DD><I>
N. Kranitis, A. Paschalis, G. Xenoulis, D. Gizopoulos, and Y. Zorian
</I><P>
<DT>
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A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]
<DD><I>
P. Bernardi, M. Rebaudengo, M. Sonza Reorda, and M. Violante
</I><P>
<DT>
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Test Data Compression: The System Integratorâs Perspective [p. 726]
<DD><I>
P. Gonciari, B. Al-Hashimi, and N. Nicolici
</I><P>
<DT>
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Time Domain Multiplexed TAM: Implementation and Comparison [p. 732]
<DD><I>
Z. Ebadi and A. Ivanov
</I><P>
<DT>
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<A HREF="../../pdffiles/08c_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization [p. 738]
<DD><I>
K. Goel and E. Marinissen
</I><P>
<DT>
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<A HREF="../../pdffiles/08c_6.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Delay Fault Testing of Core-Based Systems-On-A-Chip [p. 744]
<DD><I>
Q. Xu and N. Nicolici
</I><P>
</DL>
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<H2>8D: <A HREF="dateabs.htm#sess8d" NAME="sess8d">
Synthesis and Analysis of Digital Circuits
</A></H2>
<I>
Moderators: W. Kunz, Kaiserslautern U, DE; T. Villa, Udine U, IT
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Reducing Multi-Valued Algebraic Operations to Binary [p. 752]
<DD><I>
J. Jiang, R. Brayton, and A. Mishchenko
</I><P>
<DT>
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Combination of Lower Bounds in Exact BDD Minimization [p. 758]
<DD><I>
R. Ebendt, W. Gnther, and R. Drechsler
</I><P>
<DT>
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Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits:
An Application in Power Estimation [p. 764]
<DD><I>
A. Freitas and A. Oliveira
</I><P>
<DT>
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<A HREF="../../pdffiles/08d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information [p. 770]
<DD><I>
U. Seidl, F. Johannes, and K. Eckl
</I><P>
</DL>
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<H2>8E: <A HREF="dateabs.htm#sess8e" NAME="sess8e">
Embedded System Architectures (Embedded Software Forum)
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<I>
Moderators: W. Fornaciari, Politecnico di Milano, IT; T. Thurner, DaimlerChrysler Research, DE
</I><P>
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Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology [p. 778]
<DD><I>
A. Agarwal, T. Vijaykumar, and K. Roy
</I><P>
<DT>
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Enhancing Speedup in Network Processing Applications by Exploiting Instruction
Reuse with Flow Aggregation [p. 784]
<DD><I>
G. Surendra, S. Banerjee, and S. Nandy
</I><P>
<DT>
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On-Chip Stochastic Communication [p. 790]
<DD><I>
T. Dumitras and R. Marculescu
</I><P>
<DT>
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<A HREF="../../pdffiles/08e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Integrated Approach for Improving Cache Behavior [p. 796]
<DD><I>
G. Memik, A. Choudhary, M. Kandemir, and I. Kadayif
</I><P>
<DT>
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<A HREF="../../pdffiles/08e_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Rapid Configuration and Instruction Selection for an ASIP: A Case Study [p. 802]
<DD><I>
N. Cheung, S. Parameswaran, and J. Henkel
</I><P>
</DL>
<HR>
<H2>8F: <A HREF="dateabs.htm#sess8f" NAME="sess8f">
Specification and Verification in Action
</A></H2>
<I>
Moderators: W. Ecker, Infineon, DE; T. Kropf, Robert Bosch GmbH, DE
</I><P>
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Local Search for Boolean Relations on the Basis of Unit Propagation [p. 810]
<DD><I>
Y. Novikov
</I><P>
<DT>
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<A HREF="../../pdffiles/08f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis [p. 816]
<DD><I>
A. Goel and R. Bryant
</I><P>
<DT>
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<A HREF="../../pdffiles/08f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Preimage Computation Using a Novel Success-Driven ATPG [p. 822]
<DD><I>
S. Sheng and M. Hsiao
</I><P>
<DT>
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<A HREF="../../pdffiles/08f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using Formal Techniques to Debug the AMBA System-On-Chip Bus Protocol [p. 828]
<DD><I>
A. Roychoudhury, T. Mitra, and S. Karri
</I><P>
<DT>
<A HREF="dateabs.htm#08f_5"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08f_5.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions [p. 834]
<DD><I>
A. Ziv
</I><P>
</DL>
<HR>
<H2>9A: <A HREF="dateabs.htm#sess9a" NAME="sess9a">
Hot Topic: RF Design Technology for Highly Integrated Communication Systems
</A></H2>
<I>
Organizer/Moderator: R. Wittmann, Nokia, DE<BR>
Speakers:<BR>
J. Hartung, Cadence, DE<BR>
H.-J. Wassener, Atmel, DE<BR>
G. Trnkle, Infineon, DE<BR>
M. Schrter, CEDIC, DE
</I><P>
<DL>
<DT>
<A HREF="dateabs.htm#09a"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Panel Statement [p. 842]
</DL>
<HR>
<H2>9B: <A HREF="dateabs.htm#sess9b" NAME="sess9b">
Zoning Chip Estate
</A></H2>
<I>
Moderators: C. Sechen, Washington U, US; I. Markov, Michigan U, US
</I><P>
<DL>
<DT>
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<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique [p. 850]
<DD><I>
K. Wang and M. Marek-Sadowska
</I><P>
<DT>
<A HREF="dateabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A New and Efficient Congestion Evaluation Model in Floorplanning:
Wire Density Control with Twin Binary Trees [p. 856]
<DD><I>
S. Wai, E. Young, and C. Chu
</I><P>
<DT>
<A HREF="dateabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Crosstalk Reduction in Area Routing [p. 862]
<DD><I>
R. Smey, P. Madden, and B. Swartz
</I><P>
<DT>
<A HREF="dateabs.htm#09b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Area Fill Generation with Inherent Data Volume Reduction [p. 868]
<DD><I>
Y. Chen, A. Kahng, Y. Zheng, G. Robins, and A. Zelikovsky
</I><P>
</DL>
<HR>
<H2>9C: <A HREF="dateabs.htm#sess9c" NAME="sess9c">
Panel: Transaction Based Design:
Another Buzzword or the Solution to a Design Problem?
</A></H2>
<I>
Organizer: H.-J. Schlebusch, Synopsys, DE<BR>
Moderator: G. Smith, Gartner Dataquest, US<BR>
Panellists:<BR>
D. Sciuto, Politecnico di Milano, IT<BR>
D. Gajski, UC Irvine, US<BR>
C. Mielenz, Infineon Technologies, DE<BR>
C.K. Lennard, ARM, UK<BR>
F. Ghenassia, STMicroelectronics, FR<BR>
S. Swan, Cadence, US<BR>
J. Kunkel, Synopsys, US<BR>
</I><P>
<DL>
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Panel Statement [p. 876]
</DL>
<HR>
<H2>9D: <A HREF="dateabs.htm#sess9d" NAME="sess9d">
Trust in SAT-Based Verification?
</A></H2>
<I>
Moderators: R. Drechsler, Bremen U, DE; C. Pixley, Synopsys, US
</I><P>
<DL>
<DT>
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<A HREF="../../pdffiles/09d_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Validating SAT Solvers Using an Independent Resolution-Based Checker:
Practical Implementations and other Applications [p. 880]
<DD><I>
L. Zhang and S. Malik
</I><P>
<DT>
<A HREF="dateabs.htm#09d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Verification of Proofs of Unsatisfiability for CNF Formulas [p. 886]
<DD><I>
E. Goldberg and Y. Novikov
</I><P>
<DT>
<A HREF="dateabs.htm#09d_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]
<DD><I>
F. Lu, L. Wang, K. Cheng, and R. Huang
</I><P>
<DT>
<A HREF="dateabs.htm#09d_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals [p. 898]
<DD><I>
G. Cabodi, S. Nocco, and S. Quer
</I><P>
</DL>
<HR>
<H2>9E: <A HREF="dateabs.htm#sess9e" NAME="sess9e">
Transformations for Real-Time Software (Embedded Software Forum)
</A></H2>
<I>
Moderators: L. Thiele, ETH Zurich, CH; Z. Peng, Linkping U, SE
</I><P>
<DL>
<DT>
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<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generalized Data Transformations for Enhancing Cache Behavior [p. 906]
<DD><I>
V. De La Luz, M. Kandemir, I. Kadayif, and U. Sezer
</I><P>
<DT>
<A HREF="dateabs.htm#09e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Software Streaming via Block Streaming [p. 912]
<DD><I>
P. Kuacharoen, V. Mooney, and V. Madisetti
</I><P>
<DT>
<A HREF="dateabs.htm#09e_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 918]
<DD><I>
Y. Zhang and K. Chakrabarty
</I><P>
</DL>
<HR>
<H2>9F1: <A HREF="dateabs.htm#sess9f1" NAME="sess9f1">
Synthesis Tools for Asynchronous Circuits
</A></H2>
<I>
Moderators: M. Renaudin, TIMA Laboratory, FR; A. Koelmans, Newcastle U, UK
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<DT>
<A HREF="dateabs.htm#09f1_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f1_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]
<DD><I>
A. Madalinski, A. Bystrov, V. Khomenko, and A. Yakovlev
</I><P>
<DT>
<A HREF="dateabs.htm#09f1_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f1_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
STG Optimisation in the Direct Mapping of Asynchronous Circuits [p. 932]
<DD><I>
D. Sokolov, A. Bystrov, and A. Yakovlev
</I><P>
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<H2>9F2: <A HREF="dateabs.htm#sess9f2" NAME="sess9f2">
Collaborative Design and WWW-Based Tools
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<I>
Moderators: T.J. Kazmierski, Southampton U, UK; W. Mueller, C-LAB Paderborn, DE
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Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]
<DD><I>
L. Indrusiak, F. Lubitz, R. Reis, and M. Glesner
</I><P>
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Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]
<DD><I>
H. Eikerling, W. Mueller, T. Schattkowsky, and J. Wegner
</I><P>
</DL>
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<H2>10A: <A HREF="dateabs.htm#sess10a" NAME="sess10a">
Performance Optimisation in Hardware/Software Codesign
</A></H2>
<I>
Moderators: J. Madsen, TU Denmark, DK; F. Rousseau, TIMA Laboratory, FR
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Layered, Multi-Threaded, High-Level Performance Design [p. 954]
<DD><I>
A. Cassidy, J. Paul, and D. Thomas
</I><P>
<DT>
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A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with
Consideration of Mode Execution Probabilities [p. 960]
<DD><I>
M. Schmitz, B. Al-Hashimi, and P. Eles
</I><P>
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Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]
<DD><I>
G. Braun, A. Wieferink, O. Schliebusch, R. Leupers, and H. Meyr, and A. Nohl
</I><P>
</DL>
<HR>
<H2>10B: <A HREF="dateabs.htm#sess10b" NAME="sess10b">
Dynamic Resource Management for Reconfigurable Systems
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<I>
Moderators: Y. Tanurhan, Actel, US; C. Passerone, Politecnico di Torino, IT
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Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]
<DD><I>
M. Gericota, G. Alves, M. Silva, and J. Ferreira
</I><P>
<DT>
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Managing a Reconfigurable Processor in a General Purpose Workstation Environment [p. 980]
<DD><I>
M. Dales
</I><P>
<DT>
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Infrastructure for Design and Management of Relocatable Tasks in a
Heterogeneous Reconfigurable System-On-Chip [p. 986]
<DD><I>
J. Mignolet, V. Nollet, P. Coene, S. Vernalde, D. Verkest, and R. Lauwereins
</I><P>
</DL>
<HR>
<H2>10C: <A HREF="dateabs.htm#sess10c" NAME="sess10c">
Advances in Test Pattern Generation
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<I>
Moderators: S. Kundu, Intel, US; B. Straube, FhG IIS/EAS Dresden, DE
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RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]
<DD><I>
M. Santos, J. Fernandes, I. Teixeira, and J. Teixeira
</I><P>
<DT>
<A HREF="dateabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
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A New Approach to Test Generation and Test Compaction for Scan Circuits [p. 1000]
<DD><I>
I. Pomeranz and S. Reddy
</I><P>
<DT>
<A HREF="dateabs.htm#10c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]
<DD><I>
F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero
</I><P>
<DT>
<A HREF="dateabs.htm#10c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
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On the Characterization of Hard-To-Detect Bridging Faults [p. 1012]
<DD><I>
I. Pomeranz, S. Reddy, and S. Kundu
</I><P>
</DL>
<HR>
<H2>10D: <A HREF="dateabs.htm#sess10d" NAME="sess10d">
Analogue and Digital Simulation
</A></H2>
<I>
Moderators: M. Zwolinski, Southampton U, UK; P. Schwarz, FhG IIS/EAS Dresden, DE
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<DL>
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The Power Grid Transient Simulation in Linear Time Based on 3D
Alternating-Direction-Implicit Method [p. 1020]
<DD><I>
Y. Lee and C. Chen
</I><P>
<DT>
<A HREF="dateabs.htm#10d_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10d_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching [p. 1026]
<DD><I>
Z. Wang and J. Zhu
</I><P>
<DT>
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<A HREF="../../pdffiles/10d_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Fast Algorithm for the Layout Based Electro-Thermal Simulation [p. 1032]
<DD><I>
M. Rencz, V. Szkely, and A. Poppe
</I><P>
<DT>
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<A HREF="../../pdffiles/10d_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Platform Based Testbench Generation [p. 1038]
<DD><I>
R. Henftling, M. Bauer, M. Zambaldi, A. Zinn, and W. Ecker
</I><P>
</DL>
<HR>
<H2>10E: <A HREF="dateabs.htm#sess10e" NAME="sess10e">
Low Power Software (Embedded Software Forum)
</A></H2>
<I>
Moderators: M. Miranda, IMEC, BE; F. Fallah, Fujitsu, US
</I><P>
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Software Architectural Transformations: A New Approach to Low Energy Embedded Software [p. 1046]
<DD><I>
T. Tan, A. Raghunathan, and N. Jha
</I><P>
<DT>
<A HREF="dateabs.htm#10e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Dynamic Functional Unit Assignment for Low Power [p. 1052]
<DD><I>
S. Haga, N. Reeves, R. Barua, and D. Marculescu
</I><P>
<DT>
<A HREF="dateabs.htm#10e_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy [p. 1058]
<DD><I>
M. Kandemir, W. Zhang, and I. Kolcu
</I><P>
<DT>
<A HREF="dateabs.htm#10e_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors [p. 1064]
<DD><I>
D. Nicolaescu, A. Veidenbaum, and A. Nicolau
</I><P>
</DL>
<HR>
<H2>10F: <A HREF="dateabs.htm#sess10f" NAME="sess10f">
Application Specific Memory Synthesis
</A></H2>
<I>
Moderators: R. Hermida, Madrid Complutense U, ES; P. Eles, Linkping U, SE
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<A HREF="../../pdffiles/10f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]
<DD><I>
E. Brockmeyer, M. Miranda, F. Catthoor, and H. Corporaal
</I><P>
<DT>
<A HREF="dateabs.htm#10f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mesh Partitioning Approach to Energy Efficient Data Layout [p. 1076]
<DD><I>
S. Hettiaratchi and P. Cheung
</I><P>
<DT>
<A HREF="dateabs.htm#10f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
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On-Chip Stack Based Memory Organization for Low Power Embedded Architectures [p. 1082]
<DD><I>
M. Mamidipaka and N. Dutt
</I><P>
</DL>
<HR>
<H2><A HREF="dateabs.htm#poster" NAME="poster">
Poster Sessions
</A></H2>
<H2>4P: <A HREF="dateabs.htm#4p" NAME="4p">
CAD for Analogue Design, Design Methodologies and Physical Design
</A></H2>
<DL>
<DT>
<A HREF="dateabs.htm#04p_01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Figure of Merit Based Selection of A/D Converters [p. 1190]
<DD><I>
M. Vogels and G. Gielen
</I><P>
<DT>
<A HREF="dateabs.htm#04p_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines [p. 1092]
<DD><I>
O. Kraus and M. Padeffke
</I><P>
<DT>
<A HREF="dateabs.htm#04p_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Multithreaded Synchronous Data Flow Simulation [p. 1094]
<DD><I>
J. Kin and J. Pino
</I><P>
<DT>
<A HREF="dateabs.htm#04p_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs [p. 1096]
<DD><I>
K. Fazel, M. Thornton, and R. Reese
</I><P>
<DT>
<A HREF="dateabs.htm#04p_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural
Networks Using Hidden Neuron Clustering [p. 1098]
<DD><I>
S. Doboli, G. Gothoskar, and A. Doboli
</I><P>
<DT>
<A HREF="dateabs.htm#04p_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology [p. 1100]
<DD><I>
A. Deb, J.
berg, and A. Jantsch
</I><P>
<DT>
<A HREF="dateabs.htm#04p_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]
<DD><I>
J. Lo, W. Kuo, T. Hwang, and A. Wu
</I><P>
<DT>
<A HREF="dateabs.htm#04p_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration [p. 1104]
<DD><I>
W. Choi and K. Bazargan
</I><P>
<DT>
<A HREF="dateabs.htm#04p_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for
Basic Analog Building Blocks [p. 1106]
<DD><I>
A. Girardi and S. Bampi
</I><P>
<DT>
<A HREF="dateabs.htm#04p_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]
<DD><I>
A. Manthe, Z. Li, R. Shi, and K. Mayaram
</I><P>
<DT>
<A HREF="dateabs.htm#04p_11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]
<DD><I>
J. Gerling, O. Stbbe, J. Schrage, G. Mrozynski, and J. Teich
</I><P>
<DT>
<A HREF="dateabs.htm#04p_12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04p_12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A New Crosstalk Noise Model for DOMINO Logic Circuits [p. 1112]
<DD><I>
S. Choi and K. Roy
</I><P>
<DT>
<A HREF="dateabs.htm#04p_13"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Modeling Noise Transfer Characteristic of Dynamic Logic Gates [p. 1114]
<DD><I>
L. Ding and P. Mazumder
</I><P>
</DL>
<HR>
<H2>5P: <A HREF="dateabs.htm#5p" NAME="5p">
Reconfigurable Computing and Systems Design
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Heterogeneous Programmable Logic Block Architectures [p. 1118]
<DD><I>
A. Koorapaty, V. Chandra, K. Tong, C. Patel, L. Pileggi, and H. Schmit
</I><P>
<DT>
<A HREF="dateabs.htm#05p_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
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An Industrial/Academic Configurable System-On-Chip Project (CSoC):
Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]
<DD><I>
J. Becker, A. Thomas, M. Vorbach, and V. Baumgarte
</I><P>
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<A HREF="dateabs.htm#05p_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]
<DD><I>
F. Moraes, D. Mesquita, J. Palma, L. Mller, and N. Calazans
</I><P>
<DT>
<A HREF="dateabs.htm#05p_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mapping Applications to an FPFA Tile [p. 1124]
<DD><I>
M. Rosien, Y. Guo, G. Smit, and T. Krol
</I><P>
<DT>
<A HREF="dateabs.htm#05p_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]
<DD><I>
E. Nilsson, M. Millberg, J.
berg, and A. Jantsch
</I><P>
<DT>
<A HREF="dateabs.htm#05p_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Micro-Network for SoC: Implementation of a 32-Port SPIN Network [p. 1128]
<DD><I>
A. Andriahantenaina and A. Greiner
</I><P>
<DT>
<A HREF="dateabs.htm#05p_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
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A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]
<DD><I>
A. Rettberg, M. Zanella, C. Bobda, and T. Lehmann
</I><P>
<DT>
<A HREF="dateabs.htm#05p_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Library Functions Timing Characterization for Source-Level Analysis [p. 1132]
<DD><I>
C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto
</I><P>
<DT>
<A HREF="dateabs.htm#05p_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]
<DD><I>
A. Chang, W. Kuo, T. Hwang, and A. Wu
</I><P>
<DT>
<A HREF="dateabs.htm#05p_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power Constrained High-Level Synthesis of Battery Powered Systems [p. 1136]
<DD><I>
S. Nielsen and J. Madsen
</I><P>
<DT>
<A HREF="dateabs.htm#05p_11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
PARLAK: Parametrized Lock Cache Generator [p. 1138]
<DD><I>
B. Akgul and V. Mooney
</I><P>
<DT>
<A HREF="dateabs.htm#05p_12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05p_12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Secure Web-Based Framework for Electronic System Level Design [p. 1140]
<DD><I>
T. Kazmierski and X. Yang
</I><P>
</DL>
<HR>
<H2>6P: <A HREF="dateabs.htm#6p" NAME="6p">
Low Power Design and Estimation, Verification and Testing
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Background Data Organisation for the Low-Power Implementation in
Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]
<DD><I>
P. Op de Beeck, C. Ghez, E. Brockmeyer, M. Miranda, F. Catthoor, and G. Deconinck
</I><P>
<DT>
<A HREF="dateabs.htm#06p_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Compiler Support for Reducing Leakage Energy Consumption [p. 1146]
<DD><I>
W. Zhang, M. Kandemir, N. Vijaykrishnan, M. Irwin, and V. De
</I><P>
<DT>
<A HREF="dateabs.htm#06p_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries [p. 1148]
<DD><I>
P. Rong and M. Pedram
</I><P>
<DT>
<A HREF="dateabs.htm#06p_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in
Real-Time Distributed Embedded Systems [p. 1150]
<DD><I>
J. Luo, N. Jha, and L. Peh
</I><P>
<DT>
<A HREF="dateabs.htm#06p_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Decomposition of Extended Finite State Machine for Low Power Design [p. 1152]
<DD><I>
M. Lee, T. Hwang, and S. Huang
</I><P>
<DT>
<A HREF="dateabs.htm#06p_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Equisolvability of Series vs. Controllerâs Topology in Synchronous Language Equations [p. 1154]
<DD><I>
N. Yevtushenko, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli, and A. Petrenko
</I><P>
<DT>
<A HREF="dateabs.htm#06p_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using RTL Statespace Information and State Encoding for Induction Based Property Checking [p. 1156]
<DD><I>
M. Wedler, D. Stoffel, and W. Kunz
</I><P>
<DT>
<A HREF="dateabs.htm#06p_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems [p. 1158]
<DD><I>
E. Pastor and M. Pea
</I><P>
<DT>
<A HREF="dateabs.htm#06p_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in
Scaled Technologies [p. 1160]
<DD><I>
N. Sirisantana and K. Roy
</I><P>
<DT>
<A HREF="dateabs.htm#06p_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06p_10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes [p. 1162]
<DD><I>
S. Tarnick
</I><P>
<DT>
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Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and
Monitoring via Parity Trees [p. 1164]
<DD><I>
P. Drineas and Y. Makris
</I><P>
</DL>
<HR>
<H2>7P: <A HREF="dateabs.htm#7p" NAME="7p">
System Level Design and Specification and Testing Techniques
</A></H2>
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<DT>
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<A HREF="../../pdffiles/07p_01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SAT-Based Techniques in System Synthesis [p. 1168]
<DD><I>
C. Haubelt, J. Teich, R. Feldmann, and B. Monien
</I><P>
<DT>
<A HREF="dateabs.htm#07p_02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Refinement of Mixed-Signal Systems with SystemC [p. 1170]
<DD><I>
C. Grimm, C. Meise, W. Heupke, and K. Waldschmidt
</I><P>
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<A HREF="dateabs.htm#07p_03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Polychrony for Refinement-Based Design [p. 1172]
<DD><I>
J. Talpin, P. Le Guernic, S. Shukla, R. Gupta, and F. Doucet
</I><P>
<DT>
<A HREF="dateabs.htm#07p_04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]
<DD><I>
X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe
</I><P>
<DT>
<A HREF="dateabs.htm#07p_05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Consequences of RAM Bitline Twisting for Test Coverage [p. 1176]
<DD><I>
I. Schanstra and J. van de Goor
</I><P>
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<A HREF="dateabs.htm#07p_06"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_06.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme [p. 1178]
<DD><I>
F. Corsi, C. Marzocca, and G. Matarrese
</I><P>
<DT>
<A HREF="dateabs.htm#07p_07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Test Generation for Acyclic Sequential Circuits with Single Stuck-At Fault Combinational ATPG [p. 1180]
<DD><I>
H. Ichihara and T. Inoue
</I><P>
<DT>
<A HREF="dateabs.htm#07p_08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Comparison of Test Pattern Decompression Techniques [p. 1182]
<DD><I>
O. Novk
</I><P>
<DT>
<A HREF="dateabs.htm#07p_09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST [p. 1184]
<DD><I>
I. Polian, B. Becker, and S. Reddy
</I><P>
<DT>
<A HREF="dateabs.htm#07p_10"><IMG SRC="../../../../../icons/absicon.gif"></A>
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Test Data Compression Based on Output Dependence [p. 1186]
<DD><I>
I. Pomeranz and S. Reddy
</I><P>
<DT>
<A HREF="dateabs.htm#07p_11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07p_11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]
<DD><I>
V. Iyengar, A. Chandra, S. Schweizer, and K. Chakrabarty
</I><P>
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