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DATE 2001 :
[ <A HREF="datetoc.htm">Table of Contents</A> ]
[ <A HREF="dateabs.htm">Abstracts</A> ]
[ <A HREF="datesess.htm">Session Index</A> ]</H3>
<HR>
<H2>DATE 2001 Author Index</H2>
<B>
<A HREF="#A">[A]</A>
<A HREF="#B">[B]</A>
<A HREF="#C">[C]</A>
<A HREF="#D">[D]</A>
<A HREF="#E">[E]</A>
<A HREF="#F">[F]</A>
<A HREF="#G">[G]</A>
<A HREF="#H">[H]</A>
<A HREF="#I">[I]</A>
<A HREF="#J">[J]</A>
<A HREF="#K">[K]</A>
<A HREF="#L">[L]</A>
<A HREF="#M">[M]</A>
<A HREF="#N">[N]</A>
<A HREF="#O">[O]</A>
<A HREF="#P">[P]</A>
<A HREF="#Q">[Q]</A>
<A HREF="#R">[R]</A>
<A HREF="#S">[S]</A>
<A HREF="#T">[T]</A>
<A HREF="#U">[U]</A>
<A HREF="#V">[V]</A>
<A HREF="#W">[W]</A>
<A HREF="#X">[X]</A>
<A HREF="#Y">[Y]</A>
<A HREF="#Z">[Z]</A><P>
</B>
<HR>
<DL><H1><A NAME="A">A</A></H1>
<DT><B>Abadir, M. </B>
<DD>
<A HREF="dateabs.htm#07c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Full Chip False Timing Path Identification: Applications to the
PowerPC<SUP>TM</SUP> Microprocessors [p. 514]
<DT><B>Aboulhamid, E. </B>
<DD>
<A HREF="dateabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
<DT><B>Abraham, J. </B>
<DD>
<A HREF="dateabs.htm#07c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Full Chip False Timing Path Identification: Applications to the
PowerPC<SUP>TM</SUP> Microprocessors [p. 514]
<DT><B>Acosta, A. </B>
<DD>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DT><B>Acosta, A. </B>
<DD>
<A HREF="dateabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
<DT><B>Acquaviva, A. </B>
<DD>
<A HREF="dateabs.htm#05b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
<DT><B>Adler, T. </B>
<DD>
<A HREF="dateabs.htm#p25"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p25.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits
[p. 819]
<DT><B>Agrawal, V. </B>
<DD>
<A HREF="dateabs.htm#04c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Spectral Techniques for Sequential ATPG [p. 204]
<DT><B>Al-Ars, Z.</B>
<DD>
<A HREF="dateabs.htm#07c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded
DRAMs [p. 496]
<DT><B>Alba Pinto, C. </B>
<DD>
<A HREF="dateabs.htm#p30"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p30.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Constraint Satisfaction for Storage Files with Fifos or Stacks during
Scheduling [p. 824]
<DT><B>Al-Hashimi, B. </B>
<DD>
<A HREF="dateabs.htm#08b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems
Specification [p. 566]
<DT><B>Al-Hashimi, B.</B>
<DD>
<A HREF="dateabs.htm#p05"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p05.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional
Design Space [p. 802]
<DT><B>Ambler, T. </B>
<DD>
<A HREF="dateabs.htm#05c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
<DT><B>Ammer, M. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Andrews, A. </B>
<DD>
<A HREF="dateabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DT><B>Ashar, P. </B>
<DD>
<A HREF="dateabs.htm#p02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Axelsson, Jakob</B>
<DD>
<A HREF="dateabs.htm#02e_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Methods and Tools for Systems Engineering of Automotive Electronic
Architectures
<DT><B>Azaïs, F.</B>
<DD>
<A HREF="dateabs.htm#08c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Implementation of a Linear Histogram BIST for ADCs [p. 590]
<DT><B>Azuma, M. </B>
<DD>
<A HREF="dateabs.htm#04f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
</DL>
<HR>
<DL><H1><A NAME="B">B</A></H1>
<DT><B>Badaroglu, M. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Badia, R. </B>
<DD>
<A HREF="dateabs.htm#10a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
<DT><B>Baghdadi, A. </B>
<DD>
<A HREF="dateabs.htm#02a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Architecture Model for Systematic Design of Application-Specific
Multiprocessor SoC [p. 55]
<DT><B>Banerjee, P. </B>
<DD>
<A HREF="dateabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Precision and Error Analysis of MATLAB Applications during Automated
Hardware Synthesis for FPGAs [p. 722]
<DT><B>Barke, E. </B>
<DD>
<A HREF="dateabs.htm#07a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Architecture Driven Partitioning [p. 479]
<DT><B>Barke, E. </B>
<DD>
<A HREF="dateabs.htm#p11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
<DT><B>Bayraktaroglu, I. </B>
<DD>
<A HREF="dateabs.htm#02c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
<DT><B>Bazargan-Sabet, P. </B>
<DD>
<A HREF="dateabs.htm#07f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
<DT><B>Beattie, M. </B>
<DD>
<A HREF="dateabs.htm#06f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Inductance Extraction via Windowing [p. 430]
<DT><B>Behling, A. </B>
<DD>
<A HREF="dateabs.htm#p15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
Embedded Processors [p. 811]
<DT><B>Bekooij, M. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>Bekooij, M. </B>
<DD>
<A HREF="dateabs.htm#p28"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p28.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
<DT><B>Bellido, M. </B>
<DD>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DT><B>Benabdenbi, M. </B>
<DD>
<A HREF="dateabs.htm#03c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism
[p. 150]
<DT><B>Benini, L. </B>
<DD>
<A HREF="dateabs.htm#02a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Component Selection and Matching for IP-Based Design [p. 40]
<DT><B>Benini, L. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Benini, L. </B>
<DD>
<A HREF="dateabs.htm#05b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
<DT><B>Benini, L. </B>
<DD>
<A HREF="dateabs.htm#08a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
<DT><B>Benso, A. </B>
<DD>
<A HREF="dateabs.htm#04c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
<DT><B>Bernard, S. </B>
<DD>
<A HREF="dateabs.htm#08c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Implementation of a Linear Histogram BIST for ADCs [p. 590]
<DT><B>Bertoni, G. </B>
<DD>
<A HREF="dateabs.htm#p16"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p16.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Finite Field Digit-Serial Multiplier Architecture for
Cryptography Applications [p. 812]
<DT><B>Bertrand, Y. </B>
<DD>
<A HREF="dateabs.htm#08c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Implementation of a Linear Histogram BIST for ADCs [p. 590]
<DT><B>Bhadra, J. </B>
<DD>
<A HREF="dateabs.htm#07c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Full Chip False Timing Path Identification: Applications to the
PowerPC<SUP>TM</SUP> Microprocessors [p. 514]
<DT><B>Bjorkman, M. </B>
<DD>
<A HREF="dateabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DT><B>Bois, G. </B>
<DD>
<A HREF="dateabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
<DT><B>Bolsens, I. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Bolsens, I. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Braun, G. </B>
<DD>
<A HREF="dateabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generating Production Quality Software Development Tools Using a Machine
Description Language [p. 674]
<DT><B>Brayton, R. </B>
<DD>
<A HREF="dateabs.htm#03a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using SAT for Combinational Equivalence Checking [p. 114]
<DT><B>Breveglieri, L. </B>
<DD>
<A HREF="dateabs.htm#p16"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p16.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Finite Field Digit-Serial Multiplier Architecture for
Cryptography Applications [p. 812]
<DT><B>Bromley, P. </B>
<DD>
<A HREF="dateabs.htm#06e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools [p. 420]
<DT><B>Bunnbauer, W. </B>
<DD>
<A HREF="dateabs.htm#p04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Annotated Data Types for Addressed Token Passing Networks [p. 801]
<DT><B>Burdiek, B. </B>
<DD>
<A HREF="dateabs.htm#08c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using
Nonlinear Programming and Time -Domain Sensitivities [p. 603]
<DT><B>Busá, N.</B>
<DD>
<A HREF="dateabs.htm#p28"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p28.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
</DL>
<HR>
<DL><H1><A NAME="C">C</A></H1>
<DT><B>Cabodi, G. </B>
<DD>
<A HREF="dateabs.htm#01a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
<DT><B>Camurati, P. </B>
<DD>
<A HREF="dateabs.htm#01a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
<DT><B>Cappuccino, G. </B>
<DD>
<A HREF="dateabs.htm#p22"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p22.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
<DT><B>Casavant, A. </B>
<DD>
<A HREF="dateabs.htm#p02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Castelli, G. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Castro-López, R.</B>
<DD>
<A HREF="dateabs.htm#10c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
<DT><B>Catthoor, F. </B>
<DD>
<A HREF="dateabs.htm#09b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
<DT><B>Catthoor, F. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Chakrabarti, P. </B>
<DD>
<A HREF="dateabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
<DT><B>Chakrabarty, K. </B>
<DD>
<A HREF="dateabs.htm#03c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Test Data Compression and Decompression for System-on-a-Chip Using
Internal Scan Chains and Golomb Coding [p. 145]
<DT><B>Chakrabarti, A. </B>
<DD>
<A HREF="dateabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
<DT><B>Chandra, A. </B>
<DD>
<A HREF="dateabs.htm#03c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Test Data Compression and Decompression for System-on-a-Chip Using
Internal Scan Chains and Golomb Coding [p. 145]
<DT><B>Chang, C. </B>
<DD>
<A HREF="dateabs.htm#06b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
In-Place Delay Constrained Power Optmization Using Functional Symmetries
[p. 377]
<DT><B>Chang, N. </B>
<DD>
<A HREF="dateabs.htm#p13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p13.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
<DT><B>Charest, L. </B>
<DD>
<A HREF="dateabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
<DT><B>Chatterjee, A. </B>
<DD>
<A HREF="dateabs.htm#08c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
<DT><B>Chen, L. </B>
<DD>
<A HREF="dateabs.htm#04b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Microprocessor Power Analysis by Labeled Simulation [p. 182]
<DT><B>Chen, T. </B>
<DD>
<A HREF="dateabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DT><B>Chen, T. </B>
<DD>
<A HREF="dateabs.htm#06f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise [p. 451]
<DT><B>Cheng, D. </B>
<DD>
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<A HREF="../../pdffiles/04f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
[p. 233]
<DT><B>Cherubal, S. </B>
<DD>
<A HREF="dateabs.htm#08c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
<DT><B>Cheung, C. </B>
<DD>
<A HREF="dateabs.htm#04f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
[p. 233]
<DT><B>Cheung, P. </B>
<DD>
<A HREF="dateabs.htm#10f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
<DT><B>Cheynet, P. </B>
<DD>
<A HREF="dateabs.htm#05c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Chiusano, S. </B>
<DD>
<A HREF="dateabs.htm#03c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Applying the Set Covering Model to Reseeding [p. 156]
<DT><B>Choi, K. </B>
<DD>
<A HREF="dateabs.htm#10b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Performance Improvement of Multi-Processor Systems Cosimulation
Based on SW Analysis [p. 749]
<DT><B>Chojnacki, A.</B>
<DD>
<A HREF="dateabs.htm#06b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Quality Sub-Function Construction in Functional Decomposition Based on
Information Relationship Measures [p. 383]
<DT><B>Choudhary, A. </B>
<DD>
<A HREF="dateabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Precision and Error Analysis of MATLAB Applications during Automated
Hardware Synthesis for FPGAs [p. 722]
<DT><B>Cichon, G. </B>
<DD>
<A HREF="dateabs.htm#p04"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p04.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Annotated Data Types for Addressed Token Passing Networks [p. 801]
<DT><B>Ciesielski, M. </B>
<DD>
<A HREF="dateabs.htm#06c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
<DT><B>Cocorullo, G. </B>
<DD>
<A HREF="dateabs.htm#p22"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p22.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
<DT><B>Constantinides, G. </B>
<DD>
<A HREF="dateabs.htm#10f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
<DT><B>Corno, F. </B>
<DD>
<A HREF="dateabs.htm#04c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Test of Microprocessor IP Cores [p. 209]
<DT><B>Cossement, N. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Couderc, Damien </B>
<DD>
<A HREF="dateabs.htm#02e_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
AIL: description of a global electronic architecture at the vehicle scale
</DL>
<HR>
<DL><H1><A NAME="D">D</A></H1>
<DT><B>da Silva Jr., J. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Damasevicius, R. </B>
<DD>
<A HREF="dateabs.htm#p03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Two Approaches for Developing Generic Components in VHDL [p. 800]
<DT><B>Dasgupta, P. </B>
<DD>
<A HREF="dateabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
<DT><B>de la Rosa, J. </B>
<DD>
<A HREF="dateabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DT><B>De Man, H. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>De Man, H. </B>
<DD>
<A HREF="dateabs.htm#09b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
<DT><B>De Man, H. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>De Micheli, G. </B>
<DD>
<A HREF="dateabs.htm#02a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Component Selection and Matching for IP-Based Design [p. 40]
<DT><B>del Río, R. </B>
<DD>
<A HREF="dateabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DT><B>Delgado-Restituto, M.</B>
<DD>
<A HREF="dateabs.htm#10c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
<DT><B>Demir, A. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Demmeler, T. </B>
<DD>
<A HREF="dateabs.htm#02a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
<DT><B>Dessouky, M. </B>
<DD>
<A HREF="dateabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
<DT><B>Di Carlo, S. </B>
<DD>
<A HREF="dateabs.htm#03c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Applying the Set Covering Model to Reseeding [p. 156]
<DT><B>Di Carlo, S. </B>
<DD>
<A HREF="dateabs.htm#04c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
<DT><B>Di Natale, G. </B>
<DD>
<A HREF="dateabs.htm#04c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
<DT><B>Dielissen, J. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>Doboli, A. </B>
<DD>
<A HREF="dateabs.htm#08f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design i
of Embedded Systems under Power and Latency Constraints [p. 612]
<DT><B>Doboli, A. </B>
<DD>
<A HREF="dateabs.htm#p10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
<DT><B>Donnay, S. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Donnay, S. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Dorsch, R. </B>
<DD>
<A HREF="dateabs.htm#p09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using Mission Logic for Embedded Testing [p. 805]
<DT><B>Drechsler, R. </B>
<DD>
<A HREF="dateabs.htm#09f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Spectral Decision Diagrams Using Graph Transformations [p. 713]
<DT><B>Drozd, A. </B>
<DD>
<A HREF="dateabs.htm#05c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
<DT><B>Dutt, N. </B>
<DD>
<A HREF="dateabs.htm#10f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Access Pattern Based Local Memory Customization for Low Power Embedded Systems
[p. 778]
</DL>
<HR>
<DL><H1><A NAME="E">E</A></H1>
<DT><B>Eberle, W. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Economakos, G. </B>
<DD>
<A HREF="dateabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioral Synthesis with SystemC [p. 21]
<DT><B>Engels, L. </B>
<DD>
<A HREF="dateabs.htm#p28"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p28.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
<DT><B>Engels, M. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Engels, M. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Entrena, L. </B>
<DD>
<A HREF="dateabs.htm#06b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
<DT><B>Espejo, J. </B>
<DD>
<A HREF="dateabs.htm#06b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
</DL>
<HR>
<DL><H1><A NAME="F">F</A></H1>
<DT><B>Favalli, M. </B>
<DD>
<A HREF="dateabs.htm#05c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
<DT><B>Fekete, S. </B>
<DD>
<A HREF="dateabs.htm#09a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
<DT><B>Fernández, F.</B>
<DD>
<A HREF="dateabs.htm#10c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
<DT><B>Ferrandi, F. </B>
<DD>
<A HREF="dateabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
<DT><B>Ferrara, G. </B>
<DD>
<A HREF="dateabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
<DT><B>Fin, A. </B>
<DD>
<A HREF="dateabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
<DT><B>Fiori, F. </B>
<DD>
<A HREF="dateabs.htm#05f_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analysis of EME Produced by a Microcontroller Operation [p. 341]
<DT><B>Fiori, F. </B>
<DD>
<A HREF="dateabs.htm#p18"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p18.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Susceptibility of Analog Cells to Substrate Interference [p. 814]
<DT><B>Fragneto, P. </B>
<DD>
<A HREF="dateabs.htm#p16"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p16.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Finite Field Digit-Serial Multiplier Architecture for
Cryptography Applications [p. 812]
<DT><B>Fummi, F. </B>
<DD>
<A HREF="dateabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
</DL>
<HR>
<DL><H1><A NAME="G">G</A></H1>
<DT><B>Gangwal, O. </B>
<DD>
<A HREF="dateabs.htm#p24"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p24.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
<DT><B>Gao, Y. </B>
<DD>
<A HREF="dateabs.htm#07f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
<DT><B>Garbe, H. </B>
<DD>
<A HREF="dateabs.htm#05f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
<DT><B>Garnica, O. </B>
<DD>
<A HREF="dateabs.htm#p14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p14.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
<DT><B>Gauthier, L. </B>
<DD>
<A HREF="dateabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Generation and Targeting of Application Specific Operating Systems
and Embedded Systems Software [p. 679]
<DT><B>Gerfers, F. </B>
<DD>
<A HREF="dateabs.htm#06a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Design Strategy for Low-Voltage Low-Power Continuous-Time
Sigma-Delta A/D Converters [p. 361]
<DT><B>Gerlach, J. </B>
<DD>
<A HREF="dateabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Simulation Semantics of SystemC [p. 64]
<DT><B>Ghez, C. </B>
<DD>
<A HREF="dateabs.htm#09b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
<DT><B>Giani, A. </B>
<DD>
<A HREF="dateabs.htm#04c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Spectral Techniques for Sequential ATPG [p. 204]
<DT><B>Gielen, G. </B>
<DD>
<A HREF="dateabs.htm#04a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped
Exponential Signal Model [p. 169]
<DT><B>Gielen, G. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Giusto, P. </B>
<DD>
<A HREF="dateabs.htm#02a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
<DT><B>Giusto, P. </B>
<DD>
<A HREF="dateabs.htm#08b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reliable Estimation of Execution Time of Embedded Software [p. 580]
<DT><B>Gizopoulos, D. </B>
<DD>
<A HREF="dateabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
<DT><B>Goldberg, E. </B>
<DD>
<A HREF="dateabs.htm#03a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using SAT for Combinational Equivalence Checking [p. 114]
<DT><B>Goldberg, E. </B>
<DD>
<A HREF="dateabs.htm#03a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]
<DT><B>Göttsche, R. </B>
<DD>
<A HREF="dateabs.htm#05f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
<DT><B>Gravot, V. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>Greiner, A. </B>
<DD>
<A HREF="dateabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
<DT><B>Grun, P. </B>
<DD>
<A HREF="dateabs.htm#10f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Access Pattern Based Local Memory Customization for Low Power Embedded Systems
[p. 778]
<DT><B>Guo, C. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Gupta, A. </B>
<DD>
<A HREF="dateabs.htm#p02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Gupta, S. </B>
<DD>
<A HREF="dateabs.htm#p08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exact Fault Simulation for Systems on Silicon that Protects Each Core's
Intellectual Property (IP) [p. 804]
</DL>
<HR>
<DL><H1><A NAME="H">H</A></H1>
<DT><B>Hajjar, A. </B>
<DD>
<A HREF="dateabs.htm#06c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DT><B>Haldar, M. </B>
<DD>
<A HREF="dateabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Precision and Error Analysis of MATLAB Applications during Automated
Hardware Synthesis for FPGAs [p. 722]
<DT><B>Harcourt, E. </B>
<DD>
<A HREF="dateabs.htm#08b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reliable Estimation of Execution Time of Embedded Software [p. 580]
<DT><B>Harmsze, F. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>Hartenstein, R. </B>
<DD>
<A HREF="dateabs.htm#09a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Decade of Reconfigurable Computing: A Visionary Retrospective [p. 642]
<DT><B>Hashimoto, K. </B>
<DD>
<A HREF="dateabs.htm#09e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CPU for PlayStation®2 [p. 696]
<DT><B>Hashizume, M. </B>
<DD>
<A HREF="dateabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Open Defect Detection by Supply Current Test [p. 509]
<DT><B>Hering, K. </B>
<DD>
<A HREF="dateabs.htm#07a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
dlbSIM - A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
<DT><B>Hermes, B. </B>
<DD>
<A HREF="dateabs.htm#p07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs
[p. 803]
<DT><B>Hermida, R. </B>
<DD>
<A HREF="dateabs.htm#p14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p14.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
<DT><B>Hettich, G. </B>
<DD>
<A HREF="dateabs.htm#02e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Vehicle Electric/Electronic Architecture - One of the Most Important
Challenges for OEM's [p. 112]
<DT><B>Hoffmann, A. </B>
<DD>
<A HREF="dateabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generating Production Quality Software Development Tools Using a Machine
Description Language [p. 674]
<DT><B>Hoffmann, A. </B>
<DD>
<A HREF="dateabs.htm#10b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
<DT><B>Hoffmann, D. </B>
<DD>
<A HREF="dateabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Simulation Semantics of SystemC [p. 64]
<DT><B>Hoffmann, D. </B>
<DD>
<A HREF="dateabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
<DT><B>Horta, N. </B>
<DD>
<A HREF="dateabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Skill<SUP>TM</SUP>-Based Library for Retargetable Embedded Analog Cores
[p. 768]
<DT><B>Hsiao, M. </B>
<DD>
<A HREF="dateabs.htm#04c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Spectral Techniques for Sequential ATPG [p. 204]
<DT><B>Hsieh, C. </B>
<DD>
<A HREF="dateabs.htm#04b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Microprocessor Power Analysis by Labeled Simulation [p. 182]
<DT><B>Hu, B. </B>
<DD>
<A HREF="dateabs.htm#06b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
In-Place Delay Constrained Power Optmization Using Functional Symmetries
[p. 377]
<DT><B>Huang, Z. </B>
<DD>
<A HREF="dateabs.htm#10a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using
Reconfigurable Datapaths and Optimized Interconnection Networks [p. 735]
<DT><B>Huisken, J. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>Hwang, T. </B>
<DD>
<A HREF="dateabs.htm#09f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
</DL>
<HR>
<DL><H1><A NAME="I">I</A></H1>
<DT><B>Ichimiya, M. </B>
<DD>
<A HREF="dateabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Open Defect Detection by Supply Current Test [p. 509]
<DT><B>Ikumi, N. </B>
<DD>
<A HREF="dateabs.htm#09e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CPU for PlayStation®2 [p. 696]
<DT><B>Ilponse, F. </B>
<DD>
<A HREF="dateabs.htm#07f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
<DT><B>Irion, A. </B>
<DD>
<A HREF="dateabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
<DT><B>Ishihara, S. </B>
<DD>
<A HREF="dateabs.htm#09f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
<DT><B>Iyer, A. </B>
<DD>
<A HREF="dateabs.htm#04b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power Aware Microarchitecture Resource Scaling [p. 190]
</DL>
<HR>
<DL><H1><A NAME="J">J</A></H1>
<DT><B>Jacobs, E. </B>
<DD>
<A HREF="dateabs.htm#06b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
<DT><B>Janicot, V. </B>
<DD>
<A HREF="dateabs.htm#04a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
<DT><B>Jerke, G. </B>
<DD>
<A HREF="dateabs.htm#p25"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p25.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits
[p. 819]
<DT><B>Jerraya, A. </B>
<DD>
<A HREF="dateabs.htm#02a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Architecture Model for Systematic Design of Application-Specific
Multiprocessor SoC [p. 55]
<DT><B>Jerraya, A. </B>
<DD>
<A HREF="dateabs.htm#02b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Model for Describing Communication between Aggregate Objects in the
Specification and Design of Embedded Systems [p. 77]
<DT><B>Jerraya, A. </B>
<DD>
<A HREF="dateabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Generation and Targeting of Application Specific Operating Systems
and Embedded Systems Software [p. 679]
<DT><B>Jerraya, A. </B>
<DD>
<A HREF="dateabs.htm#10b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC
Design [p. 754]
<DT><B>Jess, J. </B>
<DD>
<A HREF="dateabs.htm#p30"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p30.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Constraint Satisfaction for Storage Files with Fifos or Stacks during
Scheduling [p. 824]
<DT><B>Jingnan, X. </B>
<DD>
<A HREF="dateabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Skill<SUP>TM</SUP>-Based Library for Retargetable Embedded Analog Cores
[p. 768]
<DT><B>Jochens, G. </B>
<DD>
<A HREF="dateabs.htm#p12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DT><B>John, W. </B>
<DD>
<A HREF="dateabs.htm#05f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
<DT><B>Józwiak, L.</B>
<DD>
<A HREF="dateabs.htm#06b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Quality Sub-Function Construction in Functional Decomposition Based on
Information Relationship Measures [p. 383]
<DT><B>Juan-Chico, J. </B>
<DD>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DT><B>Jung, J. </B>
<DD>
<A HREF="dateabs.htm#10b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Performance Improvement of Multi-Processor Systems Cosimulation
Based on SW Analysis [p. 749]
<DT><B>Jutman, A. </B>
<DD>
<A HREF="dateabs.htm#07a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
</DL>
<HR>
<DL><H1><A NAME="K">K</A></H1>
<DT><B>Kaiser, A. </B>
<DD>
<A HREF="dateabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
<DT><B>Kalla, P. </B>
<DD>
<A HREF="dateabs.htm#06c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
<DT><B>Karim, F. </B>
<DD>
<A HREF="dateabs.htm#06e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools [p. 420]
<DT><B>Kiefer, G. </B>
<DD>
<A HREF="dateabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
<DT><B>Kim, J. </B>
<DD>
<A HREF="dateabs.htm#p13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p13.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
<DT><B>Kogel, T. </B>
<DD>
<A HREF="dateabs.htm#10b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
<DT><B>Koh, C. </B>
<DD>
<A HREF="dateabs.htm#07f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
<DT><B>Köhler, E.</B>
<DD>
<A HREF="dateabs.htm#09a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
<DT><B>Koranne, S. </B>
<DD>
<A HREF="dateabs.htm#p24"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p24.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
<DT><B>Kralicek, P. </B>
<DD>
<A HREF="dateabs.htm#05f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
<DT><B>Krampl, G. </B>
<DD>
<A HREF="dateabs.htm#10c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
<DT><B>Kranitis, N. </B>
<DD>
<A HREF="dateabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
<DT><B>Krishna, S. </B>
<DD>
<A HREF="dateabs.htm#01a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
Descriptions [p. 4]
<DT><B>Kropf, T. </B>
<DD>
<A HREF="dateabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Simulation Semantics of SystemC [p. 64]
<DT><B>Kropf, T. </B>
<DD>
<A HREF="dateabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
<DT><B>Kruse, L. </B>
<DD>
<A HREF="dateabs.htm#p12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DT><B>Kuh, E. </B>
<DD>
<A HREF="dateabs.htm#06f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC
Trees with Lumped and Distributed Elements [p. 445]
<DT><B>Kulkarni, C. </B>
<DD>
<A HREF="dateabs.htm#09b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
[p. 686]
<DT><B>Küter, J.</B>
<DD>
<A HREF="dateabs.htm#07a_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Architecture Driven Partitioning [p. 479]
</DL>
<HR>
<DL><H1><A NAME="L">L</A></H1>
<DT><B>Lai, M. </B>
<DD>
<A HREF="dateabs.htm#04f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Slicing Tree is a Complete Floorplan Representation [p. 228]
<DT><B>Lamm, H. </B>
<DD>
<A HREF="dateabs.htm#05a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
<DT><B>Lanchares, J. </B>
<DD>
<A HREF="dateabs.htm#p14"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p14.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
<DT><B>Larsson, E. </B>
<DD>
<A HREF="dateabs.htm#03c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Integrated System-On-Chip Test Framework [p. 138]
<DT><B>Lauwereins, R. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Lavagno, L. </B>
<DD>
<A HREF="dateabs.htm#09b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generation of Minimal Size Code for Schedule Graphs [p. 668]
<DT><B>Lechner, A. </B>
<DD>
<A HREF="dateabs.htm#p07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs
[p. 803]
<DT><B>Li, J. </B>
<DD>
<A HREF="dateabs.htm#02c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Memory Fault Diagnosis by Syndrome Compression [p. 97]
<DT><B>Li, S. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Lienig, J. </B>
<DD>
<A HREF="dateabs.htm#p25"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p25.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits
[p. 819]
<DT><B>Liu, C. </B>
<DD>
<A HREF="dateabs.htm#09f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
<DT><B>Liu, S. </B>
<DD>
<A HREF="dateabs.htm#p02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Liu, X. </B>
<DD>
<A HREF="dateabs.htm#05b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Static Power Estimation Methodology for IP-Based Design [p. 280]
<DT><B>Liu, Y. </B>
<DD>
<A HREF="dateabs.htm#09f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
<DT><B>Lobachev, M. </B>
<DD>
<A HREF="dateabs.htm#05c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
<DT><B>Long, D. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>López, J.</B>
<DD>
<A HREF="dateabs.htm#p26"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p26.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
<DT><B>Löser, J.</B>
<DD>
<A HREF="dateabs.htm#07a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
dlbSIM - A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
<DT><B>Louërat, M.</B>
<DD>
<A HREF="dateabs.htm#06a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog Design for Reuse - Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
<DT><B>Luk, W. </B>
<DD>
<A HREF="dateabs.htm#10f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
<DT><B>Lyonnard, D. </B>
<DD>
<A HREF="dateabs.htm#02a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Architecture Model for Systematic Design of Application-Specific
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</DL>
<HR>
<DL><H1><A NAME="M">M</A></H1>
<DT><B>Maaß, C.</B>
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<A HREF="dateabs.htm#05c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
<DT><B>Macchiarulo, L. </B>
<DD>
<A HREF="dateabs.htm#08a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
<DT><B>Macii, A. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Macii, E. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Macii, E. </B>
<DD>
<A HREF="dateabs.htm#08a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
<DT><B>Madrid, N. </B>
<DD>
<A HREF="dateabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
<DT><B>Majauskas, G. </B>
<DD>
<A HREF="dateabs.htm#p03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Two Approaches for Developing Generic Components in VHDL [p. 800]
<DT><B>Malik, S. </B>
<DD>
<A HREF="dateabs.htm#10a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using
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<DT><B>Mandapati, A. </B>
<DD>
<A HREF="dateabs.htm#09e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Implementation of the ATI Flipper Chip [p. 697]
<DT><B>Manoli, Y. </B>
<DD>
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<A HREF="../../pdffiles/06a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Design Strategy for Low-Voltage Low-Power Continuous-Time
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<DT><B>Marchal, P. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Marculescu, D. </B>
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<A HREF="../../pdffiles/04b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power Aware Microarchitecture Resource Scaling [p. 190]
<DT><B>Marculescu, R. </B>
<DD>
<A HREF="dateabs.htm#08b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Probabilistic Application Modeling for System-Level Performance Analysis
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<DT><B>Marek-Sadowska, M.</B>
<DD>
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<A HREF="../../pdffiles/06b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
In-Place Delay Constrained Power Optmization Using Functional Symmetries
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<DT><B>Markwardt, J. </B>
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<A HREF="../../pdffiles/07a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
dlbSIM - A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
<DT><B>Marichalar, Simon </B>
<DD>
<A HREF="dateabs.htm#02e_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
AIL: description of a global electronic architecture at the vehicle scale
<DT><B>Maroufi, W. </B>
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<A HREF="dateabs.htm#03c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism
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<DT><B>Martin, G. </B>
<DD>
<A HREF="dateabs.htm#08b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Reliable Estimation of Execution Time of Embedded Software [p. 580]
<DT><B>Marzouki, M. </B>
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<A HREF="../../pdffiles/03c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism
[p. 150]
<DT><B>Mazumder, P. </B>
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<A HREF="dateabs.htm#06f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]
<DT><B>Medeiro, F. </B>
<DD>
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<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DT><B>Mesman, B. </B>
<DD>
<A HREF="dateabs.htm#p30"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p30.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Constraint Satisfaction for Storage Files with Fifos or Stacks during
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<DT><B>Metra, C. </B>
<DD>
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<A HREF="../../pdffiles/05c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
<DT><B>Meyr, H. </B>
<DD>
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<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generating Production Quality Software Development Tools Using a Machine
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<DT><B>Meyr, H. </B>
<DD>
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<A HREF="../../pdffiles/10b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
<DT><B>Minato, S. </B>
<DD>
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<A HREF="../../pdffiles/09f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
<DT><B>Miranda, M. </B>
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<A HREF="../../pdffiles/09b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Cache Conscious Data Layout Organization for Embedded Multimedia Applications
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<DT><B>Mirkhani, S. </B>
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<A HREF="dateabs.htm#p29"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p29.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated
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<DT><B>Mohaupt, T. </B>
<DD>
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A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
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System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
<DT><B>Moya, F. </B>
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A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
<DT><B>Moya, J. </B>
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A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
<DT><B>Mueller, W. </B>
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The Simulation Semantics of SystemC [p. 64]
<DT><B>Muhammad, K. </B>
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<A HREF="../../pdffiles/05b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients
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<DT><B>Mukaiyama, A. </B>
<DD>
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<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Müller, D. </B>
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<A HREF="../../pdffiles/01b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SystemC<SUP>SV</SUP> - An Extension of SystemC for Mixed Multi-Level
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<DT><B>Munn, I. </B>
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<A HREF="../../pdffiles/06c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
<DT><B>Musolino, F. </B>
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<A HREF="../../pdffiles/05f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analysis of EME Produced by a Microcontroller Operation [p. 341]
</DL>
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<DL><H1><A NAME="N">N</A></H1>
<DT><B>Nagamatsu, M. </B>
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CPU for PlayStation®2 [p. 696]
<DT><B>Naidu, S. </B>
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Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
<DT><B>Nam, G. </B>
<DD>
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A Boolean Satisfiability-Based Incremental Rerouting Approach with Application
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<DT><B>Nandi, A. </B>
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Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component
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<DT><B>Nandi, A. </B>
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<A HREF="../../pdffiles/08b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Probabilistic Application Modeling for System-Level Performance Analysis
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<DT><B>Narita, S. </B>
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<A HREF="../../pdffiles/09e_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SH-4 RISC Microprocessor for Multimedia, Game Machine [p. 699]
<DT><B>Navabi, Z. </B>
<DD>
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<A HREF="../../pdffiles/p29.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated
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<DT><B>Nayak, A. </B>
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<A HREF="dateabs.htm#10a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Precision and Error Analysis of MATLAB Applications during Automated
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<DT><B>Neau, C. </B>
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Low Complexity FIR Filters Using Factorization of Perturbed Coefficients
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<DT><B>Nebel, W. </B>
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<A HREF="../../pdffiles/p12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DT><B>Nguyen, L. </B>
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<A HREF="../../pdffiles/04a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
<DT><B>Nicolau, A. </B>
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Access Pattern Based Local Memory Customization for Low Power Embedded Systems
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<DT><B>Nicolescu, B. </B>
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System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Nicolescu, G. </B>
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<A HREF="../../pdffiles/02b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Model for Describing Communication between Aggregate Objects in the
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<DT><B>Nicolescu, G. </B>
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<A HREF="../../pdffiles/10b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC
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<DT><B>Nicolici, N. </B>
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Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional
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<DT><B>Nikolic, B. </B>
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Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Noguera, J. </B>
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A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
<DT><B>Nohl, A. </B>
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Generating Production Quality Software Development Tools Using a Machine
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<DT><B>Novikov, Y. </B>
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<A HREF="../../pdffiles/03a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]
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<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioral Synthesis with SystemC [p. 21]
<DT><B>Olbrich, M. </B>
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<A HREF="../../pdffiles/p11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
<DT><B>Olías, E.</B>
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Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
<DT><B>Omnès, T.</B>
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<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power Systems on Chips (SOCs) [p. 488]
<DT><B>Orailoglu, A. </B>
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<A HREF="dateabs.htm#02c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
<DT><B>Ouaiss, I. </B>
<DD>
<A HREF="dateabs.htm#09a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable
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</DL>
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<DL><H1><A NAME="P">P</A></H1>
<DT><B>Panagopoulos, I. </B>
<DD>
<A HREF="dateabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioral Synthesis with SystemC [p. 21]
<DT><B>Papaefthymiou, C. </B>
<DD>
<A HREF="dateabs.htm#05b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Static Power Estimation Methodology for IP-Based Design [p. 280]
<DT><B>Papakonstantinou, G. </B>
<DD>
<A HREF="dateabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioral Synthesis with SystemC [p. 21]
<DT><B>Parameswaran, S. </B>
<DD>
<A HREF="dateabs.htm#08f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Code Placement in Hardware Software Co -Synthesis to Improve Performance and
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<DT><B>Paschalis, A. </B>
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<A HREF="dateabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
<DT><B>Passerone, C. </B>
<DD>
<A HREF="dateabs.htm#09b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generation of Minimal Size Code for Schedule Graphs [p. 668]
<DT><B>Paulin, P. </B>
<DD>
<A HREF="dateabs.htm#06e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Network Processors: A Perspective on Market Requirements,
Processor Architectures and Embedded S/W Tools [p. 420]
<DT><B>Pedram, M. </B>
<DD>
<A HREF="dateabs.htm#04b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Microprocessor Power Analysis by Labeled Simulation [p. 182]
<DT><B>Pees, S. </B>
<DD>
<A HREF="dateabs.htm#09b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generating Production Quality Software Development Tools Using a Machine
Description Language [p. 674]
<DT><B>Peng, Z. </B>
<DD>
<A HREF="dateabs.htm#03c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Integrated System-On-Chip Test Framework [p. 138]
<DT><B>Peng, Z. </B>
<DD>
<A HREF="dateabs.htm#07a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
<DT><B>Peralías, E.</B>
<DD>
<A HREF="dateabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
<DT><B>Pérez-Verdú, B.</B>
<DD>
<A HREF="dateabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DT><B>Pflanz, M. </B>
<DD>
<A HREF="dateabs.htm#p15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
Embedded Processors [p. 811]
<DT><B>Phillips, J. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Piguet, C. </B>
<DD>
<A HREF="dateabs.htm#07b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power Systems on Chips (SOCs) [p. 488]
<DT><B>Pileggi, L. </B>
<DD>
<A HREF="dateabs.htm#06f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Inductance Extraction via Windowing [p. 430]
<DT><B>Pol, E. </B>
<DD>
<A HREF="dateabs.htm#p27"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p27.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
<DT><B>Pomeranz, I. </B>
<DD>
<A HREF="dateabs.htm#04c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Sequence Reordering to Improve the Levels of Compaction Achievable by Static
Compaction Procedures [p. 214]
<DT><B>Pomeranz, I. </B>
<DD>
<A HREF="dateabs.htm#07c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Definitions of the Numbers of Detections of Target Faults and their
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<DT><B>Poncino, M. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Poulakis, I. </B>
<DD>
<A HREF="dateabs.htm#01b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Behavioral Synthesis with SystemC [p. 21]
<DT><B>Prasad, M. </B>
<DD>
<A HREF="dateabs.htm#03a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using SAT for Combinational Equivalence Checking [p. 114]
<DT><B>Prayati, A. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Prinetto, P. </B>
<DD>
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<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Applying the Set Covering Model to Reseeding [p. 156]
<DT><B>Prinetto, P. </B>
<DD>
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<A HREF="../../pdffiles/04c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection
Environment [p. 219]
<DT><B>Psarakis, M. </B>
<DD>
<A HREF="dateabs.htm#02c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
</DL>
<HR>
<DL><H1><A NAME="Q">Q</A></H1>
<DT><B>Quasem, M. </B>
<DD>
<A HREF="dateabs.htm#p08"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p08.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exact Fault Simulation for Systems on Silicon that Protects Each Core's
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<DT><B>Quer, S. </B>
<DD>
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<A HREF="../../pdffiles/01a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
</DL>
<HR>
<DL><H1><A NAME="R">R</A></H1>
<DT><B>Rabaey, J. </B>
<DD>
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<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Radhakrishnan, R. </B>
<DD>
<A HREF="dateabs.htm#p01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Verification of Synthesized Designs Using Automatically Generated
Transformational Witnesses [p. 798]
<DT><B>Rahman, M. </B>
<DD>
<A HREF="dateabs.htm#05c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
<DT><B>Ramacher, U. </B>
<DD>
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<A HREF="../../pdffiles/05f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
<DT><B>Rebaudengo, M. </B>
<DD>
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<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Reda, S. </B>
<DD>
<A HREF="dateabs.htm#03a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Combinational Equivalence Checking Using Boolean Satisfiability and Binary
Decision Diagrams [p. 122]
<DT><B>Reddy, S. </B>
<DD>
<A HREF="dateabs.htm#04c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Sequence Reordering to Improve the Levels of Compaction Achievable by Static
Compaction Procedures [p. 214]
<DT><B>Reddy, S. </B>
<DD>
<A HREF="dateabs.htm#07c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Definitions of the Numbers of Detections of Target Faults and their
Effectiveness in Guiding Test Generation for High Defect Coverage [p. 504]
<DT><B>Reid, M. </B>
<DD>
<A HREF="dateabs.htm#01b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Methodology for Interfacing Open Source SystemC with a Third Party Software
[p. 16]
<DT><B>Rein, A. </B>
<DD>
<A HREF="dateabs.htm#p11"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p11.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
<DT><B>Renaudin, M. </B>
<DD>
<A HREF="dateabs.htm#07b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low-Power Systems on Chips (SOCs) [p. 488]
<DT><B>Renovell, M. </B>
<DD>
<A HREF="dateabs.htm#08c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Implementation of a Linear Histogram BIST for ADCs [p. 590]
<DT><B>Riccó, B.</B>
<DD>
<A HREF="dateabs.htm#05b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
<DT><B>Richardson, A. </B>
<DD>
<A HREF="dateabs.htm#p07"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p07.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs
[p. 803]
<DT><B>Rodríguez-Vázquez, A.</B>
<DD>
<A HREF="dateabs.htm#06a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
<DT><B>Rodríguez-Vázquez, A.</B>
<DD>
<A HREF="dateabs.htm#10c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
<DT><B>Rolain, Y. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Rona, M. </B>
<DD>
<A HREF="dateabs.htm#10c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
<DT><B>Rosenstiehl, W. </B>
<DD>
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<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Simulation Semantics of SystemC [p. 64]
<DT><B>Rosenstiel, W. </B>
<DD>
<A HREF="dateabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
<DT><B>Rousselle, C. </B>
<DD>
<A HREF="dateabs.htm#p15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
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<DT><B>Roy, K. </B>
<DD>
<A HREF="dateabs.htm#05b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients
[p. 268]
<DT><B>Roychowdhury, J. </B>
<DD>
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<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Rueda, A. </B>
<DD>
<A HREF="dateabs.htm#10c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
<DT><B>Ruf, J. </B>
<DD>
<A HREF="dateabs.htm#02b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
The Simulation Semantics of SystemC [p. 64]
<DT><B>Ruf, J. </B>
<DD>
<A HREF="dateabs.htm#10b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
<DT><B>Rutenbar, R. </B>
<DD>
<A HREF="dateabs.htm#08a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application
to FPGAs [p. 560]
</DL>
<HR>
<DL><H1><A NAME="S">S</A></H1>
<DT><B>Saglam, B. </B>
<DD>
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<A HREF="../../pdffiles/08f_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
<DT><B>Saitoh, M. </B>
<DD>
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<A HREF="../../pdffiles/04f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
<DT><B>Sakallah, K. </B>
<DD>
<A HREF="dateabs.htm#08a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application
to FPGAs [p. 560]
<DT><B>Salem, A. </B>
<DD>
<A HREF="dateabs.htm#03a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Combinational Equivalence Checking Using Boolean Satisfiability and Binary
Decision Diagrams [p. 122]
<DT><B>Sami, M. </B>
<DD>
<A HREF="dateabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DT><B>San Millán, E.</B>
<DD>
<A HREF="dateabs.htm#06b_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06b_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
<DT><B>Sangiovanni-Vincentelli, A. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Sansen, W. </B>
<DD>
<A HREF="dateabs.htm#04a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped
Exponential Signal Model [p. 169]
<DT><B>Sarkar, P. </B>
<DD>
<A HREF="dateabs.htm#07f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
<DT><B>Sawitzki, S. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>Scarsi, R. </B>
<DD>
<A HREF="dateabs.htm#04b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
<DT><B>Schmidt, E. </B>
<DD>
<A HREF="dateabs.htm#p12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DT><B>Schoukens, J. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Sciuto, D. </B>
<DD>
<A HREF="dateabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DT><B>Sciuto, D. </B>
<DD>
<A HREF="dateabs.htm#06c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Test Generation for Behaviorally Sequential Models [p. 403]
<DT><B>Sechen, C. </B>
<DD>
<A HREF="dateabs.htm#08a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Datapath Tile Placement and Routing [p. 552]
<DT><B>Serdar, T. </B>
<DD>
<A HREF="dateabs.htm#08a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Datapath Tile Placement and Routing [p. 552]
<DT><B>Shah, R. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Shamberger, J. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Sheets, M. </B>
<DD>
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<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Sheng, S. </B>
<DD>
<A HREF="dateabs.htm#04c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Spectral Techniques for Sequential ATPG [p. 204]
<DT><B>Shin, D. </B>
<DD>
<A HREF="dateabs.htm#p13"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p13.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
<DT><B>Siegmund, R. </B>
<DD>
<A HREF="dateabs.htm#01b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/01b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
SystemC<SUP>SV</SUP> - An Extension of SystemC for Mixed Multi-Level
Communication Modeling and Interface-Based System Design [p. 26]
<DT><B>Silvano, C. </B>
<DD>
<A HREF="dateabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DT><B>Sonza Reorda, M. </B>
<DD>
<A HREF="dateabs.htm#04c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Test of Microprocessor IP Cores [p. 209]
<DT><B>Sonza Reorda, M. </B>
<DD>
<A HREF="dateabs.htm#05c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Squillero, S. </B>
<DD>
<A HREF="dateabs.htm#04c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Test of Microprocessor IP Cores [p. 209]
<DT><B>Stuikys, V. </B>
<DD>
<A HREF="dateabs.htm#p03"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p03.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Two Approaches for Developing Generic Components in VHDL [p. 800]
<DT><B>Suzuoki, M. </B>
<DD>
<A HREF="dateabs.htm#09e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CPU for PlayStation®2 [p. 696]
<DT><B>Svarstad, K. </B>
<DD>
<A HREF="dateabs.htm#02b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Model for Describing Communication between Aggregate Objects in the
Specification and Design of Embedded Systems [p. 77]
</DL>
<HR>
<DL><H1><A NAME="T">T</A></H1>
<DT><B>Tago, H. </B>
<DD>
<A HREF="dateabs.htm#09e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CPU for PlayStation®2 [p. 696]
<DT><B>Takahashi, A. </B>
<DD>
<A HREF="dateabs.htm#04f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
<DT><B>Tamesada, T. </B>
<DD>
<A HREF="dateabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Open Defect Detection by Supply Current Test [p. 509]
<DT><B>Teica, E. </B>
<DD>
<A HREF="dateabs.htm#p01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Verification of Synthesized Designs Using Automatically Generated
Transformational Witnesses [p. 798]
<DT><B>Teich, J. </B>
<DD>
<A HREF="dateabs.htm#09a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
<DT><B>Terechko, A. </B>
<DD>
<A HREF="dateabs.htm#p27"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p27.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
<DT><B>Theeuwen, F. </B>
<DD>
<A HREF="dateabs.htm#p12"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p12.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Nonlinear Memory Power Modelling [p. 808]
<DT><B>Thornton, M. </B>
<DD>
<A HREF="dateabs.htm#09f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Spectral Decision Diagrams Using Graph Transformations [p. 713]
<DT><B>Thurner, T. </B>
<DD>
<A HREF="dateabs.htm#02e_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02e_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Vehicle Electric/Electronic Architecture - One of the Most Important
Challenges for OEM's [p. 112]
<DT><B>Tuan, T. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
</DL>
<HR>
<DL><H1><A NAME="U">U</A></H1>
<DT><B>Ubar, R. </B>
<DD>
<A HREF="dateabs.htm#07a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
</DL>
<HR>
<DL><H1><A NAME="V">V</A></H1>
<DT><B>Valencia, M. </B>
<DD>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DT><B>van de Goor, A. </B>
<DD>
<A HREF="dateabs.htm#07c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded
DRAMs [p. 496]
<DT><B>van der Werf, A. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>van der Werf, A. </B>
<DD>
<A HREF="dateabs.htm#p28"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p28.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Functional Units with Conditional Input/Output Behavior in VLIW Processors
[p. 822]
<DT><B>van Eijk, K. </B>
<DD>
<A HREF="dateabs.htm#p30"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p30.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Constraint Satisfaction for Storage Files with Fifos or Stacks during
Scheduling [p. 824]
<DT><B>van Eijndhoven, J. </B>
<DD>
<A HREF="dateabs.htm#p27"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p27.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
<DT><B>van Heijningen, M. </B>
<DD>
<A HREF="dateabs.htm#05f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
High-Level Simulation of Substrate Noise Generation from
Large Digital Circuits with Multiple Supplies [p. 326]
<DT><B>van Meerbergen, J. </B>
<DD>
<A HREF="dateabs.htm#05a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Power-Efficient Layered Turbo Decoder Processor [p. 246]
<DT><B>van Staveren, A. </B>
<DD>
<A HREF="dateabs.htm#p20"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p20.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
<DT><B>van Staveren, A. </B>
<DD>
<A HREF="dateabs.htm#p21"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p21.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear
Programming [p. 816]
<DT><B>Vanassche, P. </B>
<DD>
<A HREF="dateabs.htm#04a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped
Exponential Signal Model [p. 169]
<DT><B>Vandersteen, G. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Vandersteen, G. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Varea, M. </B>
<DD>
<A HREF="dateabs.htm#08b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems
Specification [p. 566]
<DT><B>Vazquez, P. </B>
<DD>
<A HREF="dateabs.htm#07a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation
Delay Model [p. 467]
<DT><B>Velazco, R. </B>
<DD>
<A HREF="dateabs.htm#05c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Vemuri, R. </B>
<DD>
<A HREF="dateabs.htm#09a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable
Computers [p. 650]
<DT><B>Vemuri, R. </B>
<DD>
<A HREF="dateabs.htm#p01"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p01.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Verification of Synthesized Designs Using Automatically Generated
Transformational Witnesses [p. 798]
<DT><B>Vemuri, R. </B>
<DD>
<A HREF="dateabs.htm#p10"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p10.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
<DT><B>Verhoeven, C. </B>
<DD>
<A HREF="dateabs.htm#p20"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p20.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
<DT><B>Verhoeven, C. </B>
<DD>
<A HREF="dateabs.htm#p21"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p21.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear
Programming [p. 816]
<DT><B>Verkest, D. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Vierhaus, H. </B>
<DD>
<A HREF="dateabs.htm#p15"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p15.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in
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<DT><B>Violante, M. </B>
<DD>
<A HREF="dateabs.htm#04c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On the Test of Microprocessor IP Cores [p. 209]
<DT><B>Violante, M. </B>
<DD>
<A HREF="dateabs.htm#05c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
<DT><B>Vital, J. </B>
<DD>
<A HREF="dateabs.htm#10c_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10c_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Skill<SUP>TM</SUP>-Based Library for Retargetable Embedded Analog Cores
[p. 768]
<DT><B>Vranken, H. </B>
<DD>
<A HREF="dateabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
</DL>
<HR>
<DL><H1><A NAME="W">W</A></H1>
<DT><B>Wahl, M. </B>
<DD>
<A HREF="dateabs.htm#05c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
From DFT to Systems Test - A Model Based Cost Optimization Tool [p. 302]
<DT><B>Wakabayashi, K. </B>
<DD>
<A HREF="dateabs.htm#p02"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p02.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
<DT><B>Wambacq, P. </B>
<DD>
<A HREF="dateabs.htm#04a_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04a_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
<DT><B>Wambacq, P. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Wang, K. </B>
<DD>
<A HREF="dateabs.htm#09f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
<DT><B>Watanabe, Y. </B>
<DD>
<A HREF="dateabs.htm#09b_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Generation of Minimal Size Code for Schedule Graphs [p. 668]
<DT><B>Wehn, N. </B>
<DD>
<A HREF="dateabs.htm#05a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
<DT><B>Werner, C. </B>
<DD>
<A HREF="dateabs.htm#05f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
<DT><B>Wilson, R. </B>
<DD>
<A HREF="dateabs.htm#08e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Managing the SoC Design Challenge with "Soft" Hardware [p. 610]
<DT><B>Wolf, W. </B>
<DD>
<A HREF="dateabs.htm#08f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Allocation and Scheduling of Conditional Task Graph in Hardware/Software
Co-Synthesis [p. 620]
<DT><B>Wong, C. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Wong, D. </B>
<DD>
<A HREF="dateabs.htm#04f_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Slicing Tree is a Complete Floorplan Representation [p. 228]
<DT><B>Wong, D. </B>
<DD>
<A HREF="dateabs.htm#07f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
<DT><B>Worm, A. </B>
<DD>
<A HREF="dateabs.htm#05a_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
<DT><B>Wörner, A. </B>
<DD>
<A HREF="dateabs.htm#05f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
<DT><B>Wright, P. </B>
<DD>
<A HREF="dateabs.htm#05e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Design Methodology for PicoRadio Networks [p. 314]
<DT><B>Wu, Y. </B>
<DD>
<A HREF="dateabs.htm#04f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/04f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
[p. 233]
<DT><B>Wunderlich, H. </B>
<DD>
<A HREF="dateabs.htm#02c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/02c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
<DT><B>Wunderlich, H. </B>
<DD>
<A HREF="dateabs.htm#03c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/03c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
On Applying the Set Covering Model to Reseeding [p. 156]
<DT><B>Wunderlich, H. </B>
<DD>
<A HREF="dateabs.htm#p09"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p09.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Using Mission Logic for Embedded Testing [p. 805]
</DL>
<HR>
<DL><H1><A NAME="X">X</A></H1>
<DT><B>Xie, Y. </B>
<DD>
<A HREF="dateabs.htm#08f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/08f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Allocation and Scheduling of Conditional Task Graph in Hardware/Software
Co-Synthesis [p. 620]
<DT><B>Xu, Q. </B>
<DD>
<A HREF="dateabs.htm#06f_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]
</DL>
<HR>
<DL><H1><A NAME="Y">Y</A></H1>
<DT><B>Yamamoto, Y. </B>
<DD>
<A HREF="dateabs.htm#09e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CPU for PlayStation®2 [p. 696]
<DT><B>Yang, B. </B>
<DD>
<A HREF="dateabs.htm#07e_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07e_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CAD for RF Circuits [p. 520]
<DT><B>Yang, P. </B>
<DD>
<A HREF="dateabs.htm#p17"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p17.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Task Concurrency Management Methodology Summary [p. 813]
<DT><B>Yildiz, E. </B>
<DD>
<A HREF="dateabs.htm#p21"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/p21.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear
Programming [p. 816]
<DT><B>Yoo, S. </B>
<DD>
<A HREF="dateabs.htm#09b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/09b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Automatic Generation and Targeting of Application Specific Operating Systems
and Embedded Systems Software [p. 679]
<DT><B>Yoo, S. </B>
<DD>
<A HREF="dateabs.htm#10b_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Performance Improvement of Multi-Processor Systems Cosimulation
Based on SW Analysis [p. 749]
<DT><B>Yoo, S. </B>
<DD>
<A HREF="dateabs.htm#10b_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/10b_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC
Design [p. 754]
<DT><B>Yotsuyanagi, H. </B>
<DD>
<A HREF="dateabs.htm#07c_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
CMOS Open Defect Detection by Supply Current Test [p. 509]
<DT><B>Yu, Q. </B>
<DD>
<A HREF="dateabs.htm#06f_3"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06f_3.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC
Trees with Lumped and Distributed Elements [p. 445]
</DL>
<HR>
<DL><H1><A NAME="Z">Z</A></H1>
<DT><B>Zaccaria, V. </B>
<DD>
<A HREF="dateabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DT><B>Zafalon, R. </B>
<DD>
<A HREF="dateabs.htm#05a_2"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/05a_2.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
<DT><B>Zeng, J. </B>
<DD>
<A HREF="dateabs.htm#07c_4"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/07c_4.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
Full Chip False Timing Path Identification: Applications to the
PowerPC<SUP>TM</SUP> Microprocessors [p. 514]
<DT><B>Zeng, Z. </B>
<DD>
<A HREF="dateabs.htm#06c_1"><IMG SRC="../../../../../icons/absicon.gif"></A>
<A HREF="../../pdffiles/06c_1.pdf"><IMG SRC="../../../../../icons/pdficon.gif"></A>
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
<DT><B>Zergainoh, N. </B>
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An Efficient Architecture Model for Systematic Design of Application-Specific
Multiprocessor SoC [p. 55]
<DT><B>Zhang, T. </B>
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Component Selection and Matching for IP-Based Design [p. 40]
<DT><B>Zhu, J. </B>
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MetaRTL: Raising the Abstraction Level of RTL Design [p. 71]
<DT><B>Zhu, J. </B>
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Static Memory Allocation by Pointer Analysis and Coloring [p. 785]
<DT><B>Ziberkas, G. </B>
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Two Approaches for Developing Generic Components in VHDL [p. 800]
<DT><B>Zolfy, M. </B>
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Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated
Concurrent Fault Simulation [p. 823]
<DT><B>Zorian, Y. </B>
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Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
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